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rev. 4202d?scr?06/05 1 features ? clock controller ? 80c51 core with 6 clocks per instruction ? 8 mhz on-chip oscillator ? pll for generating clock to supply cpu core, usb and smart card interfaces ? programmable cpu clock from 500 khz / x1 to 48 mhz / x1 ? reset controller ? power on reset (por) feature avoi ding an external reset capacitor ? power fail detector (pfd) ? watch-dog timer ? power management ? two power saving modes : idle and power down ? four power down wake-up sources : smart card detection, keyboard interrupt, usb resume, external interrupt ? input voltage range : 3.6v - 5.5v ? core?s power consumption (wit hout smart card and usb) : ?30 ma maximum operating current @ 48 mhz / x1 ?200 a maximum power-down current @ 5.5v ? interrupt controller ? up to 9 interrupt sources ? up to 4 level priority ? memory controller ? internal program memory : ?up to 32kb of flash or cram or rom for at8xc5122 ?up to 30kb of rom for at83c5123 ? internal data memory : 768 bytes including 256 bytes of data and 512 bytes of xram ? optional : internal data e2prom 512 bytes ? two 16-bit timer/counters ? usb 2.0 full speed interface ? 48 mhz dpll ? on-chip 3.3v usb voltage regulator and transceivers ? software detach feature ? 7 endpoints programmable with in or out direct ions and iso, bulk or interrupt transfers : ?endpoint 0: 32 bytes bidirectionnal fifo for control transfers ?endpoints 1,2,3: 8 bytes fifo ?endpoints 4,5: 64 bytes fifo ?endpoint 6: 2*64 bytes fifo with pin-pong feature ? iso 7816 uart interface fully compliant with emv, gie-cb and whql standards ? programmable iso clock from 1 mhz to 4.8 mhz ? card insertion/removal detection with automatic deactivation sequence ? programmable baud rate generator from 372 to 11.625 clock pulses ? synchronous/asynchronous protocols t=0 an d t=1 with direct or inverse convention ? automatic character repe tition on parity errors ? 32 bit waiting time counter ? 16 bit guard time counter ? internal step up/down converter with programmable voltage output : ?1.8v-30 ma, 3v-60 ma and 5v-60 ma ? current overload protection ? 6 kv esd (mil/std 833 class 3) protection on whole smart card interface ? alternate smart card interface with clk, io and rst ? uart interface with integrated baud rate generator (brg) ? keyboard interface with up to 20x8 matrix management capability ? master/slave spi interface ? four 8 bit ports, one 6 bit port, one 3-bit port ? up to seven led outputs with 3 level programmable current source : 2, 4 and 10 ma ? two general purpose i/o programmable as external interrupts ? up to 8 input lines programmable as interrupts ? up to 30 output lines c51 microcontroller with usb and smart card reader interfaces at83c5122 at83ec5122 AT85C5122 at89c5122 at89c5122ds at83c5123 at83ec5123
2 at8xc5122/23 4202d?scr?06/05 reference documents the user must get the following additionnal documents which are not included but which complete this pr oduct datasheet ? product errata sheet ? bootloader datasheet
3 at8xc5122/23 4202d?scr?06/05 product description at8xc5122/23 products are high-performance cmos derivatives of the 80c51 8-bit microcontrollers designed for usb smart card reader applications. the at8xc5122 is proposed in four versions : - rom version with or without internal data e2prom. the rom device is only factory programmable. - cram version without internal data e2 prom. the cram device implements a vola- tile program memory which is programmed by means of an embedded romed bootloader which transfers the code from a remote software programming tool called flip through uart or usb interfaces. - flash version without internal data e2prom. at power-up, the program located in the flash memory is transferred into the cram then executed. the at83c5123 is a low pin count of the at8xc5122 and is proposed in rom version with or without internal data e2prom. the rom device is only factory programmable. the at8xc5122ds is a secure version of the at8xc5122 on which the external pro- gram memory access mode is disabled.
4 at8xc5122/23 4202d?scr?06/05 note: the plcc28 pinout is common to at8xc5122 and at83c5123 products table 1. product versions features at83c5122 at83ec5122 AT85C5122 at89c5122 at89c5122ds at83c5123 at83ec5123 packages vqfp64 qfn64 plcc28 die form vqfp64 plcc28 plcc68 vqfp64 plcc28 die form vqfp64 qfn64 plcc28 vqfp64 qfn64 vqfp32 qfn32 plcc28 die form qfn32 vqfp32 plcc28 program memory 32kb rom 30kb rom 32kb cram 32kb e2prom 32kb e2prom 30kb rom 30kb rom internal data e2prom no 512 bytes no no no no 512 bytes embedded bootloader no no yes yes yes no no features vqfp32, qfn32 packages features not available : - keyboard interface - master/slave spi interface - external program memory access reduced features : - only 12 i/o with up to 4 led outputs with programmable current plcc68, vqfp64,qfn64 packages all features are available all features are available except external program memory access plcc28 package features not available : - alternate smart card interface - keyboard interface - master/slave spi interface - external program memory access reduced features : - only 7 i/o with up to 4 led outputs with programmable current
5 at8xc5122/23 4202d?scr?06/05 at8xc5122 block diagram at83c5123 block diagram dc/dc conv erter li cvcc cvss uart interf ace txd rxd 16-bit ti mer s t[0-1] interrupt controller int[0-1] alternate card crst1 cclk1 cio1 3.3 v regulator vcc vss watch-dog por pfd reset rst pll pllf xta l 1 xta l 2 8 mhz oscillator 256 x 8 ram 512 x 8 xr a m 80c51 8-bit core 256 x 8 ram internal address and data bus 32k x 8 rom (1) 32k x 8 e2prom (1) 32k x 8 cram (1) external mem ory controller ea psen ale a[8-15] ad[0-7] wr r d d+ d- vref usb interf ace iso 7816 interface cclk crst cpres cc8 cc4 cio 3.3v regulator avss avcc dvcc note 1 : the implementation of these f eatures depends on product v ersions 512 x 8 e2prom (1) parallel i/o ports p0[0-7] 8-bit port 8-bit port p2[0-7] 8-bit port p3[0-7] 6-bit port p4[0-5] 8-bit port p5[0-7] led's led[0-6] 3-bit port p1[2,6-7] spi interf ace miso mosi sck ss kbd interf ace kb[0-7] dc/dc conv erter li cvcc cvss uart interf ace txd rxd 16-bit ti mer s t[0-1] interrupt controller int[0-1] alternate card crst1 cclk1 cio1 3.3 v regulator vcc vss watch-dog por pfd reset rst pll pllf xta l 1 xta l 2 8 mhz oscillator 256 x 8 ram 512 x 8 xr a m 80c51 8-bit core 256 x 8 ram internal address and data bus 30k x 8 rom 512 x 8 e2prom (1) parallel i/o ports 8-bit port p3[0-7] d+ d- vref usb interf ace iso 7816 interface cclk crst cpres cc8 cc4 cio 3.3v regulator avss avcc dvcc note 1 : the implementation of these f eatures depends on product v ersions 1-bit port p5.0 led's led[0-3] 3-bit port p1[2,6-7]
6 at8xc5122/23 4202d?scr?06/05 pinout high pin count package description at8xc5122 version figure 1. vqfp64 package pinout 62 61 60 59 58 63 57 56 55 54 53 p0.1/ad1 p0.3/ad3 p0.5/ad5 p0.7/ad7 d+ p4.1/mosi p4.0/miso p4.2/sck p4.5/led6 p3.1/txd p4.3/led4 p4.4/led5 p3.6/wr/led2 d- xtal1 xtal2 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 crst cclk li p2.3/a11 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 vqfp64 64 52 12 13 36 37 vcc vss p5.0/kb0 p3.7/rd/led3 51 50 avss 49 avcc p3.3/int1 35 33 34 p3.4/t0/led1 p3.5/t1/crst1 cvcc 14 15 16 cvss 31 32 p0.0/ad0 p1.2/cpres p0.2/ad2 p0.4/ad4 p0.6/ad6 p1.6/ss p2.7/a15 p2.6/a14 p1.7/cclk1 p5.1/kb1 p5.2/kb2 p5.3/kb3 p5.4/kb4 p5.5/kb5 p5.6/kb6 p5.7/kb7 p3.2/int0/led0/cio1 cc4 pllf ale psen dvcc cc8 cio p3.0/rxd 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vref ea rst
7 at8xc5122/23 4202d?scr?06/05 figure 2. plcc68 package pinout (for engineering purpose only) 18 17 16 15 14 13 11 p0.1/ad1 p0.3/ad3 p0.5/ad5 p0.7/ad7 d+ p4.1/mosi p4.0/miso p4.2/sck p4.5/led6 cc8 p4.3/led4 p4.4/led5 p3.6/wr/led2 d- xtal2 xtat1 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 p3.1/txd cclk li p2.3/a11 plcc68 vcc vss p5.0/kb0 p3.7/rd/led3 avss avcc p3.3/int1 p3.4/t0/led1 p3.5/t1/crst1 cvcc cvss cio p0.0/ad0 p3.0/rxd p0.2/ad2 p0.4/ad4 p0.6/ad6 p1.6/ss p2.7/a15 p2.6/a14 p1.7/cclk1 p5.1/kb1 p5.3/kb3 p5.4/kb4 p5.5/kb5 p5.6/kb6 p5.7/kb7 p3.2/int0/led0/cio1 vref cc4 pllf ale psen dvcc p1.2/cpres crst n/a n/a 16867 66 65 64 63 62 61 2 3 4 5 6 7 8 9 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 12 19 20 21 22 24 25 26 35 36 37 38 39 40 41 42 43 34 33 32 31 30 29 28 27 23 nc nc ea rst p5.2/kb2 nc : not connected n/a : not available
8 at8xc5122/23 4202d?scr?06/05 figure 3. qfn64 package pinout 62 61 60 59 58 63 57 56 55 54 53 p0.1/ad1 p0.3/ad3 p0.5/ad5 p0.7/ad7 d+ p4.1/mosi p4.0/miso p4.2/sck p4.5/led6 p3.1/txd p4.3/led4 p4.4/led5 p3.6/wr/led2 d- xtal1 xtal2 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 crst cclk li p2.3/a11 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 qfn64 64 52 12 13 36 37 vcc vss p5.0/kb0 p3.7/rd/led3 51 50 avss 49 avcc p3.3/int1 35 33 34 p3.4/t0/led1 p3.5/t1/crst1 cvcc 14 15 16 cvss 31 32 p0.0/ad0 p1.2/cpres p0.2/ad2 p0.4/ad4 p0.6/ad6 p1.6/ss p2.7/a15 p2.6/a14 p1.7/cclk1 p5.1/kb1 p5.2/kb2 p5.3/kb3 p5.4/kb4 p5.5/kb5 p5.6/kb6 p5.7/kb7 p3.2/int0/led0/cio1 cc4 pllf ale psen dvcc cc8 cio p3.0/rxd 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vref ea rst
9 at8xc5122/23 4202d?scr?06/05 at89c5122ds version figure 4. vqfp64 package pinout 62 61 60 59 58 63 57 56 55 54 53 p0.1/ad1 p0.3/ad3 p0.5/ad5 p0.7/ad7 d+ p4.1/mosi p4.0/miso p4.2/sck p4.5/led6 p3.1/txd p4.3/led4 p4.4/led5 p3.6/wr/led2 d- xtal1 xtal2 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 crst cclk li p2.3/a11 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 vqfp64 64 52 12 13 36 37 vcc vss p5.0/kb0 p3.7/rd/led3 51 50 avss 49 avcc p3.3/int1 35 33 34 p3.4/t0/led1 p3.5/t1/crst1 cvcc 14 15 16 cvss 31 32 p0.0/ad0 p1.2/cpres p0.2/ad2 p0.4/ad4 p0.6/ad6 p1.6/ss p2.7/a15 p2.6/a14 p1.7/cclk1 p5.1/kb1 p5.2/kb2 p5.3/kb3 p5.4/kb4 p5.5/kb5 p5.6/kb6 p5.7/kb7 p3.2/int0/led0/cio1 cc4 pllf ale psen dvcc cc8 cio p3.0/rxd 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vref vcc rst
10 at8xc5122/23 4202d?scr?06/05 figure 5. qfn64 package pinout 62 61 60 59 58 63 57 56 55 54 53 p0.1/ad1 p0.3/ad3 p0.5/ad5 p0.7/ad7 d+ p4.1/mosi p4.0/miso p4.2/sck p4.5/led6 p3.1/txd p4.3/led4 p4.4/led5 p3.6/wr/led2 d- xtal1 xtal2 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 crst cclk li p2.3/a11 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 qfn64 64 52 12 13 36 37 vcc vss p5.0/kb0 p3.7/rd/led3 51 50 avss 49 avcc p3.3/int1 35 33 34 p3.4/t0/led1 p3.5/t1/crst1 cvcc 14 15 16 cvss 31 32 p0.0/ad0 p1.2/cpres p0.2/ad2 p0.4/ad4 p0.6/ad6 p1.6/ss p2.7/a15 p2.6/a14 p1.7/cclk1 p5.1/kb1 p5.2/kb2 p5.3/kb3 p5.4/kb4 p5.5/kb5 p5.6/kb6 p5.7/kb7 p3.2/int0/led0/cio1 cc4 pllf ale psen dvcc cc8 cio p3.0/rxd 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vref rst vcc
11 at8xc5122/23 4202d?scr?06/05 low pin count package description at8xc5122 and at83c5123 versions figure 6. plcc28 package pinout at83c5123 version figure 7. vqfp32 package pinout cio plcc28 p3.1/txd cclk vss cc4 dvcc cc8 xtal1 xtal2 li vcc p3.7/led3 cvcc cvss p3.6/led2 crst p3.3/int1 p1.2/cpres d- d+ avcc avss pllf p3.2/int0/led0 p3.4/t0/led1 p3.0/rxd 1 2 3 4282726 5 6 7 8 9 10 11 25 24 23 22 21 20 19 15 14 13 12 16 17 18 vref rst cio vqfp32 p3.1/txd cclk p5.0 cc4 dvcc cc8 xtal1 li vcc p3.7/led3 cvcc cvss p3.6/led2 crst p1.2/cpres d- d+ avcc avss pllf p3.4/t0/led1 p3.0/rxd 28 27 26 1 2 3 4 5 6 7 24 23 22 21 20 19 18 12 11 10 9131415 vss 8 16 17 p1.6 p3.5/t1/crst1 p1.7/cclk1 vref 25 29 30 31 32 xtal2 rst p3.2/int0/led0/cio1 p3.3/int1
12 at8xc5122/23 4202d?scr?06/05 figure 8. qfn32 package pinout cio qfn32 p3.1/txd cclk p5.0 cc4 dvcc cc8 xtal1 li vcc p3.7/led3 cvcc cvss p3.6/led2 crst p1.2/cpres d- d+ avcc avss pllf p3.4/t0/led1 p3.0/rxd 28 27 26 1 2 3 4 5 6 7 24 23 22 21 20 19 18 12 11 10 9131415 vss 8 16 17 p1.6 p3.5/t1/crst1 p1.7/cclk1 vref 25 29 30 31 32 xtal2 rst p3.2/int0/led0/cio1 p3.3/int1
13 at8xc5122/23 4202d?scr?06/05 pin description table 2. pin description port vqfp64 vqfp32 plcc68 plcc28 qfn64 qfn32 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led p0.0 30 - 41 - 30 - vcc 2kv i/o float ad0 p0 kb_out push-pull p0.1 29 - 40 - 29 - vcc 2kv i/o float ad1 p0 kb_out push-pull p0.2 28 - 39 - 28 - vcc 2kv i/o float ad2 p0 kb_out push-pull p0.3 27 - 38 - 27 - vcc 2kv i/o float ad3 p0 kb_out push-pull p0.4 25 - 36 - 25 - vcc 2kv i/o float ad4 p0 kb_out push-pull p0.5 24 - 35 - 24 - vcc 2kv i/o float ad5 p0 kb_out push-pull p0.6 23 - 34 - 23 - vcc 2kv i/o float ad6 p0 kb_out push-pull p0.7 22 - 33 - 22 - vcc 2kv i/o float ad7 p0 kb_out push-pull cio 64 32 9 4 64 32 cvcc 6kv i/o 0 port51 cvcc inactive at reset. esd tested with a 10f on cvcc an external pull-up of 10k is recommended to support icc?s with too high internal pull-ups. cc4 3 3 12 7 3 3 cvcc 6kv i/o 0 port51 cvcc inactive at reset esd tested with a 10f on cvcc p1.2 2 2 11 6 2 2 vcc 2kv i/o 1 cpres port51 weak & medium pull-up can be disconnected cc4 9 5 18 9 9 5 cvcc 6kv i/o 0 port51 cvcc inactive at reset esd tested with a 10f on cvcc cclk 12 6 21 10 12 6 cvcc 6kv o 0 push-pull cvcc inactive at reset esd tested with a 10f on cvcc crst 6 4 15 8 6 4 cvcc 6kv o 0 push-pull cvcc inactive at reset esd tested with a 10f on cvcc p1.6 47 23 58 - 47 23 vcc 2kv i/o 1 ss port51 p1.7 62 31 7 - 62 31 vcc 2kv i/o 1 cclk1 port51 p2.0 58 - 3 - 58 - vcc 2kv i/o 1 a8 port51 push-pull kb_out input wpu p2.1 57 - 2 - 57 - vcc 2kv i/o 1 a9 port51 push-pull kb_out input wpu p2.2 56 - 1 - 56 - vcc 2kv i/o 1 a10 port51 push-pull kb_out input wpu p2.3 52 - 65 - 52 - vcc 2kv i/o 1 a11 port51 push-pull kb_out input wpu p2.4 51 - 64 - 51 - vcc 2kv i/o 1 a12 port51 push-pull kb_out input wpu p2.5 50 - 63 - 50 - vcc 2kv i/o 1 a13 port51 push-pull kb_out input wpu
14 at8xc5122/23 4202d?scr?06/05 p2.6 49 - 62 - 49 - vcc 2kv i/o 1 a14 port51 push-pull kb_out input wpu p2.7 46 - 57 - 46 - vcc 2kv i/o 1 a15 port51 push-pull kb_out input wpu p3.0 45 22 56 24 45 22 vcc 2kv i/o 1 rxd port51 push-pull kb_out input wpu p3.1 48 24 59 25 48 24 vcc 2kv i/o 1 txd port51 push-pull kb_out input wpu p3.2 43 20 54 23 43 20 vcc 2kv i/o 1 int0 port51 led0 p3.3 41 19 52 22 41 19 vcc 2kv i/o 1 int1 port51 push-pull kb_out input wpu p3.4 39 18 50 21 39 18 vcc 2kv i/o 1 t0 port51 push-pull kb_out input wpu led1 p3.5 44 21 55 - 44 21 vcc 2kv i/o 1 t1 port51 p3.6 36 17 47 20 36 17 vcc 2kv i/o 1 wr port51 led2 p3.7 26 13 37 16 26 13 vcc 2kv i/o 1 rd port51 led3 p4.0 42 - 53 - 42 - vcc 2kv i/o 1 miso port51 p4.1 40 - 51 - 40 - vcc 2kv i/o 1 mosi port51 p4.2 38 - 49 - 38 - vcc 2kv i/o 1 sck port51 p4.3 37 - 48 - 37 - vcc 2kv i/o 1 port51 push-pull kb_out input mpu led4 p4.4 35 - 46 - 35 - vcc 2kv i/o 1 port51 push-pull kb_out input mpu led5 p4.5 33 - 44 - 33 - vcc 2kv i/o 1 port51 push-pull kb_out input mpu led6 p5.0 14 7 23 - 14 7 vcc 2kv i/o 1 kb0 port51 push-pull input mpu input wpu p5.1 13 - 22 - 13 - vcc 2kv i/o 1 kb1 port51 push-pull input mpu input wpu p5.2 11 - 20 - 11 - vcc 2kv i/o 1 kb2 port51 push-pull input mpu input wpu p5.3 10 - 19 - 10 - vcc 2kv i/o 1 kb3 port51 push-pull input wpd input wpu p5.4 8 - 17 - 8 - vcc 2kv i/o 1 kb4 port51 push-pull input wpd input wpu table 2. pin description (continued) port vqfp64 vqfp32 plcc68 plcc28 qfn64 qfn32 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led
15 at8xc5122/23 4202d?scr?06/05 p5.5 7 - 16 - 7 - vcc 2kv i/o 1 kb5 port51 push-pull input wpd input wpu p5.6 5 - 14 - 5 - vcc 2kv i/o 1 kb6 port51 push-pull input wpd input wpu p5.7 4 - 13 - 4 - vcc 2kv i/o 1 kb7 port51 push-pull input wpd input wpu rst 34 16 45 19 34 16 vcc i/0 reset input the port pins are driven to th eir reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal 10k pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and vss. asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. the output is active for at least 12 oscillator periods when an internal reset occurs. d+ 60 29 5 2 60 29 dvcc i/o usb positive data upstream port this pin requires an external serial resistor of 27 ? (at8xc122) or 33 ? (at83c5123) and a 1.5 k ? pull-up to v ref for full speed configuration. d- 59 28 4 1 59 28 dvcc i/o usb negative data upstream port this pin requires an external serial resistor of 27 ? (at8xc122) or 33 ? (at83c5123) v ref 61 30 6 3 61 30 avcc o usb voltage reference : 3.0 < v ref < 3.6 v v ref can be connected to d+ through a 1.5 k ? resistor. the v ref voltage is controlled by software. xtal 1 31 14 42 17 31 14 vcc i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crys tal or an external oscillator must be connected to this pin. xtal 2 32 15 43 18 32 15 vcc o output of the on-chip inve rting oscillator amplifier to use the internal oscillator, a crystal circuit must be connected to this pin. if an external oscillat or is used, leave xtal2 unconnected. ea / vcc 63 - 8 - 63 - vcc i external access enable (only at8xc5122) ea must be strapped to ground in order to enable the device to fetch code from external memory locations 0000h to ffffh. if security level 1 is programmed, ea will be latched on reset. warning : ea pin cannot be left floati ng. if the external access enable mode is not used, ea pin must be strapped to vcc. if this last condition is not met,the mcu ma y have an unpredictable behaviour. vcc (only at89c5122ds) ale21-32-21- vcc o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (1/3 in x2 mode) the oscillator frequency, and c an be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ale can be disabled by setting sfr?s auxr.0 bit. with this bit set, ale will be inactive during internal fetches table 2. pin description (continued) port vqfp64 vqfp32 plcc68 plcc28 qfn64 qfn32 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led
16 at8xc5122/23 4202d?scr?06/05 psen 15 - 24 - 15 - vcc o program strobe enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. pllf 54 26 67 27 54 26 avcc o pll low pass filter input receives the rc network of the pll low pass filter. avcc 55 27 68 28 55 27 pwr analog supply voltage avcc is used to supply the inter nal 3.3v analog regulator which supplies the internal usb driver vcc 20 12 31 15 20 12 pwr supply voltage vcc is used to supply the inter nal 3.3v digital regulator which supplies the pll, cpu core and internal i/o?s li 18 10 29 13 18 10 pwr dc/dc input li supplies the current for the charge pump of the dc/dc converter. - li tied directly to vcc : the dc/dc converter must be configured in regulator mode. - li tied to vcc through an external 10h coil : the dc/dc converter can be configured either in regulator or in pump mode. cvcc 17 9 28 12 17 9 pwr card supply voltage cvcc is the ouput of internal dc/ dc converter which supplies the smart card interface. it must be connected to an external decoupling capacitor of 10 f with the lowest esr as this parameter influences on the cvcc noise dvcc 1 1 10 5 1 1 pwr digital supply voltage dvcc is the output of the internal analog 3.3v regulator which supplies the usb driver. this pin must be connected to an external 680nf decoupling capacitor if the usb interface is used. this output can be used by the applic ation with a maximum of 10 ma. cvss 19 11 30 14 19 11 gnd dc/dc ground cvss is used to sink high shunt currents from the external coil vss 16 8 25 11 16 8 gnd digital ground vss is used to supply the pll, buffer ring and the digital core avss 53 25 66 26 53 25 gnd analog ground avss is used to supply the usb driver. table 2. pin description (continued) port vqfp64 vqfp32 plcc68 plcc28 qfn64 qfn32 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led
17 at8xc5122/23 4202d?scr?06/05 typical applications recommended external components all the external components described in the figure and table below must be imple- mented as close as possible from the microcontroller package. table 3. external components bill of materials reference description value comments r1 usb full speed pull-up 1.5 k ? +/-10% all product versions r2 usb pad serial resistor 27 ? +/-10% for at8xc5122 versions 33 ? +/-10% for at83c5123 versions r3 usb pad serial resistor 27 ? +/-10% for at8xc5122 versions 33 ? +/-10% for at83c5123 versions r4 pll filter resistor 1.8 k ? +/-10% all product versions r5 cio pull-up resistor 10 k ? +/10% all product versions c1 power supply filter capacitor 100 nf +80/-20% all product versions c2 pll filter capacitor 33 pf +/-10% all product versions c3 pll filter capacitor 150 pf +/-10% all product versions c4 usb pad decoupling capacitor 680 nf +/-30% all product versions. if usb interface is not used, this capacitor is optional c5 smart card clock filter capacito r 27 pf +/-10% all product versions. c6 dc/dc converter decoupling capacitor 10 f +/-10% low esr all product versions. this capacitor does not impact the usb inrush current c7 dc/dc converter filter capacito r 100 nf +80/-20% all product versions c8 power supply decoupling capacitor 4.7 f +/-10% all products versions this capacitor impacts the usb inrush current. maximum application capacitance allowed by the usb standard is 10 f. c9 power supply filter capacitor 100 nf +80/-20c all product versions c10 reset capacitor 10 f +/-10% opti onal capacitor for all product versions l1 dc/dc converter input inductance 10 h +/- 10% min rated current : 200 ma min rated freq. : 4 mhz all product versions. qualified component : murata lqh32cn100k21l if dc/dc converter is not used at 5v, this inductance is optional. q1 crystal 8.0000 mhz +/- 2500 ppm max esr max : 100 ? all product versions
18 at8xc5122/23 4202d?scr?06/05 usb keyboard with smart card reader using the at8xc5122 and at89c5122ds versions ledx vcc kb1 kb2 kb3 kb4 kb5 kb6 kb7 r19 r18 r17 r16 r15 p3[0-1,3-4] p2[0-7] r14 r13 r12 r11 r10 r09 r08 p0[0-7] r07 r06 r05 r04 r03 r02 r01 r00 keyboard matrix c1 c2 c3 c4 c5 c6 c7 kb0 c0 gnd c1 ea/vcc (1) gnd gnd c8 c9 vcc vcc vcc avcc xtal2 xtal1 q1 vcc r2 gnd d- d+ vref d+ d- vcc vbus gnd usb r3 r1 avss gnd c2 r4 c3 pllf vss gnd gnd c4 dvcc 10ma max gnd cclk1 crst1 cio1 rst clk i/o c2 c3 c7 vcc c1 gnd c5 alternate card vcc gnd rst optional capacitor c10 notes : 1 - pin configuration depends on product versions li l1 smart card c1 c2 c3 c4 c7 c8 c5 vcc rst clk c4 i/o c8 gnd s1 cpres s2 gnd gnd c6 s1 c7 cc8 cio cc4 cclk crst cvss cvcc vcc r5
19 at8xc5122/23 4202d?scr?06/05 usb smart card reader us ing the at83c5123 version ledx vcc gnd rst optional capacitor gnd gnd c1 ea gnd gnd c8 c9 vcc vcc vcc avcc xtal2 xtal1 q1 vcc r2 gnd d- d+ vref d+ d- vcc vbus gnd usb r3 r1 c10 cclk1 crst1 cio1 rst clk i/o c2 c3 c7 vcc c1 gnd c5 alternate card avss gnd c2 r4 c3 pllf vss gnd gnd c4 dvcc 10ma max vcc li l1 smart card c1 c2 c3 c4 c7 c8 c5 vcc rst clk c4 i/o c8 gnd s1 cpres s2 gnd gnd c6 s1 c7 cc8 cio cc4 cclk crst cvss cvcc vcc r5
20 at8xc5122/23 4202d?scr?06/05 memory organization the at8xc5122/23 devices have separated address spaces for program and data memory, as shown in figure 13 on page 29, figure 14 on page 31 and figure 15 on page 32. the logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an-bit cpu. neverthele ss, 16-bit data memory addresses can also be generated through the dptr register. program memory managament depending on the state of ea pin, the mcu fe tches the code from internal or external program memory (romless mode) warning : the ea pin can not be left floating, otherwise mcu may have an unpredict- able behaviour. if ea is strapped to vcc, the mcu fetches the code from the internal program memory. the way the mcu works in this mode depends on the device version. see next para- graphs for further details. if the ea is strapped to gnd, the mcu fetches the code from external program memory. this mode is common for all device versions wich supports it. after reset, the cpu begins the execution from location 0000h. there can be up to 64 kbytes of program memory. in this mode, the internal program memories are disabled. the hardware configuration for external program execution is shown in figure 9. figure 9. executing from external program memory note that the 16 i/o lines (ports 0 and 2) are dedicated to bus functions during external program memory fetches. port 0 serves as a multiplexed address/dat bus. it emits the low byte of the program counter (pcl) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. during the time that the low byte of the program counter is valid on p0, the signal ale (address latch enable) clocks the byte into an address latch. meanwhile, port 2 emits the high byte of the pro- gram counter (pch). then psen strobes the external program memory and the code byte is read into the mcu. psen is not activated and ports p0 and p2 are not affected during internal program fetches. external program memory at8xc5122 p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale latch oe psen#
21 at8xc5122/23 4202d?scr?06/05 data memory managament all device versions implements : - 256 bytes of ram to increase data parameter handling and high level language usage - 512 bytes of xram (extended ram) to store program data. ram achitecture the internal ram is mapped into three separate segments : ? the lower 128 bytes (addresses 00h to 7fh) are directly and indirectly addressable. ? the upper 128 bytes (addresses 80h to ffh) are indirectly addressable only. ? the special function registers (sfrs) (addresses 80h to ffh) are directly addressable only. the upper 128 bytes and sfr?s have the same address space but are physically separated. when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is in the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. ? instructions that use direct addressi ng access sfr space. for example: mov 0a0h, # data, accesses the sfr at location 0a0h (which is p2). ? instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0, # data where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be lo cated in the xram. the m0 bit allows to stretch the xram timi ngs. if m0 is set, the read and write pulses are extended from 6 to 30 clock periods. this is useful to access external slow peripherals. xram achitecture depending on the state of extram bit in au xr register (see table 5 on page 24), the mcu fetches data from inte rnal or external xram. if extram=0 (reset condition) , the mcu fetches the data fr om internal xram. the size of internal xram is configured by the bi t xrs0 in auxr register (see table 5 on page 24). the xram logically occupies the first bytes of external data memory. the bit xrs0 can be used to hide a part of the available xram . this can be useful if external peripherals are mapped at addresses already used by the internal xram. the xram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. for example, movx @r0, # data where r0 contains 0a0h, accesses the xram at address 0a0h rather than external memory. table 4. xram size configuration xrs0 xram size address start end 0 256 bytes (reset condition) 000h 0ffh 1 512 bytes 000h 1ffh
22 at8xc5122/23 4202d?scr?06/05 an access to external xram memory locations higher than the accessible size of the memory (roll-over fe ature) will be performed with the movx dptr instructions, with p0 and p2 as data/address busses, wr and rd as respectively write and read signals. accesses above xram size can on ly be done by the use of dptr. if extram=1 the mcu fetches the data from external xram memory. there can be up to 64 kbytes of external xram memory. the hardware configuration for external data memory access is shown in figure 10 figure 10. accessing to extern al xram memory movx @ri and movx @dptr will be similar to the standard 80c51. movx @ ri will provide an eight-bit address multiplexed wit h data on port 0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a sixteen-bit address. port 2 outputs the high- order eight address bits (dph) while port0 multiplexes the low-order eight address bits (dpl) with data. movx @ ri an d movx @dptr will generate ei ther read or write sig- nals on w r and r d . ports p0, p2 are not affected and rd, wr signals are not activated during access to internal xram. note that external xram memory access is only available on high pin count packages. external program memory and external xram memory may be combined if desired by applying the rd and psen signals to the inputs of an and gate and us ing the ouput of the gate as the read strobe to the external program/data memory. dual data pointer register (ddptr) the additional data pointer can be used to speed up code exec ution and reduce code size. the dual dptr structure is a way by which the chip will spec ify the address of an exter- nal data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = au xr1.0 (see table 7) t hat allow the program code to switch between them (figure 11). external xram memory at8xc5122/23 p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale wr oe rd# wr# latch rd psen strobe
23 at8xc5122/23 4202d?scr?06/05 figure 11. use of dual pointer a. bit 2 stuck at 0; this allows to use in c auxr1 to toggle dps without changing gf3. assembly language ; block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 qu 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ;increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a par- ticular state, but simply toggl es it. in simple routines, su ch as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. for example, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruction (i nc auxr1), the routine will exit with dps in the opposite state. external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1
24 at8xc5122/23 4202d?scr?06/05 registers reset value = 0xxx x000b table 5. auxiliary register - auxr (8eh) 76543210 dpu - - - xrs0 extram ao bit number bit mnemonic description 7dpu disable weak pull-up 0 weak pull-up is enabled 1 weak pull-up is disabled 6-3 - reserved the value read from this bit is i ndeterminate. do not change these bits. 2xrs0 xram size 0 256 bytes (default) 1 512 bytes 1 extram extram bit cleared to access internal xram using movx @ ri/ @ dptr. set to access external memory. programmed by hardware after power-up regarding hardware security byte (hsb), default setting , xram selected. 0ao ale output bit cleared , ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used)(default). set , ale is active only when a mo vx or movc instruction is used.
25 at8xc5122/23 4202d?scr?06/05 table 6. auxiliary register 1 auxr 1- (0a2h) for at8xc5122 reset value = xx1x xx0x0b (not bit addressable) table 7. auxiliary register 1 auxr 1- (0a2h) for at83c5123 reset value = xxxx xx0x0b (not bit addressable) 7 6 5 4 3 2 1 0 - - enboot - gf3 0 - dps bit number bit mnemonic description 7 - 6 - reserved the value read from this bit is indeterminate. do not change these bits. 5enboot enable boot rom (cram / e2prom version only) set this bit to map the boot rom from 8000h to ffffh. if the pc increments beyond 7fffh address, the code is fetch from internal rom clear this bit to disable boot rom. if the pc increments beyond 7fffh address, the code is fetch from external code memory (c51 standard roll over function) this bit is forced to 1 at reset 4- reserved the value read from this bit is indeterminate. do not change this bit. 3 gf3 this bit is a general-purpose user flag. 2 0 always cleared. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0dps data pointer selection cleared to select dptr0. set to select dptr1. 7 6 5 4 3 2 1 0 ----gf30-dps bit number bit mnemonic description 7 - 6 - reserved the value read from this bit is indeterminate. do not change these bits. 5 reserved the value read from this bit is indeterminate. do not change these bits. 4- reserved the value read from this bit is indeterminate. do not change this bit. 3 gf3 this bit is a general-purpose user flag. 2 0 always cleared. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0dps data pointer selection cleared to select dptr0. set to select dptr1.
26 at8xc5122/23 4202d?scr?06/05 reset value = xxxx 0xxxb at8xc5122?s cram and e2prom versions the at8xc5122?s cram and e2prom versions implements : - 32 kb of rom mapped from 8000 to ffff in which is embedded a bootloader for in- system programming feature - 32 kb of cram (code ram) , a volatile program memory mapped from 0000 to 7fff in cram versions only : - 512 bytes of e2prom can be optionally implemented to store permanent data in e2prom version : - 32kb of e2prom are implemented to store permanent code warnings : ? some bytes of user program memory space are reserved for bootloader configuration. depending on the configur ation, up to 256 bytes of code may be not available for the user code from 7f00h location. refer to bootloader datasheet for further details. ? port p3.7 may be used by the bootloader as a hardware condition at reset to select the in-system programming mode. once the bootloader has started, the p3.7 port is no more used. table 8. cram configuration register - rcon (d1h) 76543210 ----rps--- bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is i ndeterminate. do not change these bits. 3rps cram memory mapping bit set to map the cram memory during movx instructions clear to map the xram memory during movx. this bit has priority over the extram bit. 2-0 - reserved the value read from this bit is i ndeterminate. do not change these bits.
27 at8xc5122/23 4202d?scr?06/05 when pin ea =1 and after the reset, the mcu begins the execution of the embedded bootloader from location f800h of the rom. the bootloader implements an in-system programming (isp) mode which manages the tr ansfer of the code in the volatile pro- gram memory (cram). for cram version, the code is supplied by the atmel?s flexible in-system program- ming software (flip) through usb or uart interface for e2prom version, the code is supplied fr om the internal code e2prom or by flip. the state of pin p3.7 at reset determines the code source. if p3.7=1 (reset condition) the source is the internal e2prom and the transfer takes about 1.5 seconds. if p3.7=0 the source is flip and the transfer time depends mainly on external conditions not related to bootloader. once the code is running in cram, the roll-over condition (code fetched beyond address 7fffh) depends on the state of en boot bit of auxr1 register (table 6 on page 25). if enboot=1 (reset condition) the mcu fetches the code from bootloader rom. if enboot=0, the mcu fetches the code from the external program memory. in this last case, psen is activated and ports p0 and p2 are used to emit data and address signals. warning : external program memory access is not allowed on low pin count packages. 7fffh 0000h 7effh 7f00h reserved user code bootloader ffffh p3.7 at8xc5122 microcontroller
28 at8xc5122/23 4202d?scr?06/05 using cram memory the cram is a read / write volatile memory that is mapped in the program memory space. then when the power is switched off the code is lost and needs to be reload at each power up. in retu rn, the cram enables a lot of fl exibility in the code development as it can be programmed indefinitely. the user code running in the cram can perform read operations in cram itself by means of movc instructions like any c51 microcon- troller does. although the writing operati ons in cram are usually handled by the bootloader, it is possib le for the user code to handle its own writing operations in cram as well. the user code must call api functions provided by the bootloader in the rom memory. refer to bootloader datasheet for fu rther details about the use of these api functions. these api functions use a mechanism provided by the at8xc5122 microcon- troller. when the bit rps is set in rco n register (table 8 on page 26), the movx intructions are configured to write in cram instead of xram memory. however, due to c51 architecture, it is not possible for the user code to write directly in cram when it is itself running in cram. this is why the api f unctions must be called in order to have the code executing in rom wh ile the cram is written. figure 12. read / write mechanisms in cram memory movx api functions rps=1 read operation writing operation user code cram bootloader api call movc
29 at8xc5122/23 4202d?scr?06/05 figure 13. at8xc5122?s cram and e2prom versions reset@ <0000> ea = 0 program external program psen reset@ 0000 7fff 8000 ffff 32k rom 32k cram ea = 1 internal internal 32k program external enboot=1 enboot=0 8000 ffff memory on-chip 512 bytes xram 0000 01ff ffff rd wr data memory (read / write) 0000 extram=0 extram=1 external external xram xram 01ff 0200 psen roll-over roll-over memory memory 32k internal e2prom (read/write) (read only) (read/write) sfr space 80 ff 00 7f 80 ff upper 128 bytes ram lower 128 bytes ram on-chip 256 bytes ram direct addressing indirect addressing 512 bytes internal e2prom 01ff 0000 optional ffff 8000 (applicable only to cram version) (e2prom version)
30 at8xc5122/23 4202d?scr?06/05 at8xc5122?s rom version the at8xc5122?s rom version implements : - 32 k of rom mapped from 0000h to 7fffh in which is embedded the user code. the rom device is only factory programmable. - 512 bytes of e2prom can be optionally implemented to store permanent data. with this option, the size of rom is reduced to 30k. after the reset, the mcu begins the execution of the user code from location 0000h of the rom. access to external program memory is not allowed. security level there are two security levels (applicab le to high pin count packages only) : the security level 2 can be used to protect th e user code from piracy. this option is con- figured at factory and must be reques ted by the customer at order time. table 9. security levels description security level protection description 1 no protection lock enabled 2 movc instruction executed from external program memory is disabled when fetching code bytes from internal program memory ea is sampled and latched on reset. external code execution is enabled.
31 at8xc5122/23 4202d?scr?06/05 figure 14. at8xc5122?s rom version program memory (read only) 0000 7fff ffff ea=1 internal 32k rom ea=0 external external reset@ <0000> sfr space 80 ff on-chip 512 bytes xram 0000 01ff ffff rd wr 00 7f 80 ff upper 128 bytes ram lower 128 bytes ram data memory (read / write) 0000 extram=0 extram=1 external external xram xram 01ff 0200 8000 roll-over psen on-chip 256 bytes ram direct addressing indirect addressing 512 bytes internal e2prom 01ff 0000 optional roll-over
32 at8xc5122/23 4202d?scr?06/05 at83c5123 version the at83c5123 device is a low pin count version of the at8xc5122. the rom version implements : - 30 kb of rom mapped from 0000 to 77ff in which is embedded the user code. the rom device is only factory programmable. - 512 bytes of e2prom can be optionally implemented to store permanent data figure 15. at83c5123?s device program memory (read only) 7fff internal 30k rom reset@ <0000> sfr space 80 ff on-chip 512 bytes xram 0000 01ff 00 7f 80 ff upper 128 bytes ram lower 128 bytes ram data memory (read / write) on-chip 256 bytes ram direct addressing indirect addressing 512 bytes internal e2prom 01ff 0000 optional
33 at8xc5122/23 4202d?scr?06/05 special function registers (sfr?s) introduction the special function registers (sfrs) of the at8xc5122/23 can be ranked into the fol- lowing categories: ? c51 core registers: acc, b, dph, dpl, psw, sp ? system configuration re gisters: pcon, ckrl, ckcon0, ckcon1, cksel, pllcon, plldiv, auxr, auxr1, rcon ? i/o port registers: p0, p1, p2, p3, p4, p5, pmod1, pmod2 ? timer registers: tcon, th0, th1, tmod, tl0, tl1 ? watchdog (wd) registers: wdtrst, wdtprg ? serial i/o port registers: saddr, saden, sbuf, scon ? baud rate generator (brg) registers: brl, bdrcon ? system interrupt registers: ie 0, ipl0, iph0, ie1, ipl1, iph1 ? smart card interface (sci) register s: scsr, sccon/scetu0, scisr/scetu1, scier/sciir, scibuf, scgt0/scwt0, scgt1/scwt1, scicr/scwt2, sciclk ? dc/dc converter registers: dcckps ? keyboard interface re gisters: kbe, kbf, kbls ? serial port interface (spi) re gisters: spcon, spsta, spdat ? universal serial bus (usb) regist ers:usbcon, usbaddr, usbint, usbien, uepnum, uepconx, uepstax, uepr st, uepint, uepien, uepdatx, ubyctx, ufnuml, ufnumh ? led controller registers: ledcon0, ledcon1
34 at8xc5122/23 4202d?scr?06/05 at8xc5122 version notes: 1. mapping is done using scrs bit in scsr register. 2. grey areas : do not write in. bit addressable not bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 f0h b 0000 0000 ledcon0 0000 0000 e8h p5 1111 1111 e0h acc 0000 0000 ledcon1 xx00 0000 ubyctx 0000 0000 d8h d0h psw 0000 0000 rcon xxxx 0xxx uepconx 1000 0000 ueprst 0000 0000 c8h uepstax 0000 0000 uepdatx 0000 0000 s c r s 1 c0h p4 1111 1111 sciclk (1) 0x10 1111 uepien 0000 0000 spcon 0001 0100 spsta 0000 0000 spdat 1111 1111 usbaddr 1000 0000 uepnum 0000 0000 0 scwt3 (1) 0000 0000 b8h ipl0 x000 000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0000 0000 dcckps 0000 0000 s c r s 1 b0h p3 1111 1111 ien1 xxxx x000 ipl1 00xx 00x0 iph1 00xx 00x0 scgt0 (1) 0000 1100 scgt1 (1) xxxx xxx0 scicr (1) 0000 0000 iph0 x000 0000 0 scwt0 (1) 1000 0000 scwt1 (1) 0010 0101 scwt2 (1) 0000 0000 s c r s 1 a8h ien0 0000 0000 saddr 0000 0000 scibuf xxxx xxxx scsr x000 1000 scetu0 (1) 0111 0100 scetu1 (1) xxxx x001 scier (1) 0x00 0000 0 sccon (1) 0000 0000 scisr (1) 10x0 0000 sciir (1) 0x00 0000 a0h p2 1111 1111 isel 0000 0100 auxr1 xx1x 0xx0 pllcon xxxx x000 plldiv 0000 0000 wdtrst xxxx xxxx wdtprg xxxx x000 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 kbls 0000 0000 kbe 0000 0000 kbf 0000 0000 90h p1 1111 1111 pmod0 (2) 0000 0000 ckrl xxxx 1111 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0xxx x000 ckcon0 x0x0 x000 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pmod1 0000 0000 cksel xxxx xxx0 pcon 00x1 0000
35 at8xc5122/23 4202d?scr?06/05 at83c5123 version notes: 1. mapping is done using scrs bit in scsr register. 2. grey areas : do not write in. bit addressable not bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 f0h b 0000 0000 ledcon0 0000 0000 e8h p5 xxxx xxx1 e0h acc 0000 0000 ubyctx 0000 0000 d8h d0h psw 0000 0000 uepconx 1000 0000 ueprst 0000 0000 c8h uepstax 0000 0000 uepdatx 0000 0000 s c r s 1 c0h p4 11xx xxxx sciclk (1) 0x10 1111 uepien 0000 0000 usbaddr 1000 0000 uepnum 0000 0000 0 scwt3 (1) 0000 0000 b8h ipl0 x000 000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0000 0000 dcckps 0000 0000 s c r s 1 b0h p3 1111 1111 ien1 x0xx 0xxx ipl1 x0xx 0xxx iph1 x0xx 0xxx scgt0 (1) 0000 1100 scgt1 (1) xxxx xxx0 scicr (1) 0000 0000 iph0 x000 0000 0 scwt0 (1) 1000 0000 scwt1 (1) 0010 0101 scwt2 (1) 0000 0000 s c r s 1 a8h ien0 0000 0000 saddr 0000 0000 scibuf xxxx xxxx scsr x000 1000 scetu0 (1) 0111 0100 scetu1 (1) xxxx x001 scier (1) 0x00 0000 ckcon1 xxxx xxx0 0 sccon (1) 0000 0000 scisr (1) 10x0 0000 sciir (1) 0x00 0000 a0h isel 0000 0100 auxr1 xxxx 0xx0 pllcon xxxx x000 plldiv 0000 0000 wdtrst xxxx xxxx wdtprg xxxx x000 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 90h p1 1111 1111 pmod0 00xx 0xxx ckrl xxxx 1111 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0xxx x000 ckcon0 x0x0 x000 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 pmod1 xxxx 00xx cksel xxxx xxx0 pcon 00x1 0000
36 at8xc5122/23 4202d?scr?06/05 sfr?s description note: 1. only for at8xc5122 note: 1. only for at8xc5122 table 10. c51 core sfrs mnemonicaddname 76543210 acc e0h accumulator acc b f0h b register b psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp 81h stack pointer sp dpl 82h data pointer low byte (lsb of dptr) dpl dph 83h data pointer high byte (msb of dptr) dph table 11. clock sfrs mnemonicaddname 76 5 43210 pcon 87h power controller smod1 smod0 pof gf1 gf0 pd idl ckcon0 8fh clock controller 0 wdx2 six2 t1x2 t0x2 x2 ckcon1 afh clock controller 1 spix2 cksel 85h clock selection cks ckrl 97h clock reload register ckrel 3-0 pllcon a3h pll controller register ext48 pllen plock plldiv a4h pll divider register r3-0 n3-0 auxr 8eh auxiliary register 0 dpu xrs0 extram a0 auxr1 a2h auxiliary register 1 enboot (1) gf3 dps rcon (1) d1h cram memory configuration rps table 12. i/o port sfrs mnemonic add name 7 6 5 4 3 2 1 0 p0 (1) 80h port 0 p0 p1 90h port 1 p1 p2 (1) a0h port 2 p2 p3 b0h port 3 p3 p4 (1) c0h port 4 p4 p5 e8h port 5 p5 (only p5.0 for at8xc5122) pmod0 91h port mode register 0 p3c1 p3c0 p2c1 (1) p2c0 (1) cpresres - p0c1 (1) p0c0 (1) pmod1 84h port mode register 1 p5hc1 (1) p5hc0 (1) p5mc1 (1) p5mc0 (1) p5lc1 p5lc0 p4c1 (1) p4c0 (1)
37 at8xc5122/23 4202d?scr?06/05 table 13. timers sfrs mnemonicaddname 76543210 th0 8ch timer/counter 0 high byte th0 tl0 8ah timer/counter 0 low byte tl0 th1 8dh timer/counter 1 high byte th1 tl1 8bh timer/counter 1 low byte tl1 tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 table 14. watchdog sfrs mnemonicaddname 76543210 wdtrst a6h watchdog timer reset wdtrst wdtprg a7h watchdog timer program s2-0 table 15. serial i/o ports sfrs mnemonicaddname 76543210 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf 99h serial data buffer sbuf saden b9h slave address mask saden saddr a9h slave address saddr table 16. baud rate generator sfrs mnemonicaddname 76543210 brl 9ah baud rate reload brl bdrcon 9bh baud rate control brr tbck rbck spd m0src table 17. interrupt sfrs mnemonicaddname 76543210 ien0 a8h interrupt enable control 0 ea es et1 ex1 et0 ex0 ien1 b1h interrupt enable control 1 eusb esci espi (1) ekb (1) ipl0 b8h interrupt priority control low 0 psl pt1l px1l pt0l px0l
38 at8xc5122/23 4202d?scr?06/05 note: 1. only for at8xc5122 iph0 b7h interrupt priority control high 0 psh pt1h px1h pt0h px0h ipl1 b2h interrupt priority control low 1 pusbl pscil pspil (1) pkbl (1) iph1 b3h interrupt priority control high 1 pusbh pscih pspih (1) pkbh (1) isel a1h interrupt enable register cplev presit rxit oelev oeen presen rxen table 17. interrupt sfrs mnemonicaddname 76543210 table 18. scib sfrs mnemonicaddname 76543210 scgt0 b4h smart card transmit guard time register 0 gt7 - 0 scgt1 b5h smart card transmit guard time register 1 gt8 scwt0 b4h smart card character/ block waiting time register 0 wt7 - 0 scwt1 b5h smart card character/ block waiting time register 1 wt15-8 scwt2 b6h smart card character/ block waiting time register 2 wt23-16 scwt3 c1h smart card character/ block waiting time register 3 wt31-24 scicr b6h smart card interface control register reset carddet vcard1-0 uart wten crep conv sccon ach smart card interface contacts register clk cardc8 cardc4 cardio cardclk cardrst cardvcc scetu0 ach smart card etu register 0 etu7 - 0 scetu1 adh smart card etu register 1 comp etu10-8 scisr adh smart card uart interface status register (read only) sctbe cardin icardovf vcardok scwto sctc scrc scpe sciir aeh smart card uart interrupt identification register (read only) sctbi icarderr vcarderr scwti scti scri scpi scier aeh smart card uart interrupt enable register esctbi icarder evcarder escwti escti escri escpi scsr abh smart card selection register bgten crepsel altkps1-0 scclk1 scrs scibuf aah smart card buffer register can store a new byte to be transmitted on the i/o pin when sctbe is set. bit ordering on the i/o pin depends on the convention provides the byte received from the i/o pin when s cri is set. bit ordering on the i/o pin depends on the convention.
39 at8xc5122/23 4202d?scr?06/05 note: 1. only for at8xc5122 note: 1. only for at8xc5122 notes: 1. only for at8xc5122 sciclk c1h smart card frequency prescaler register xtscs (1) sciclk5-0 table 18. scib sfrs mnemonicaddname 76543210 table 19. dc/dc sfrs mnemonicaddname 76543210 dcckps bfh dc/dc converter reload register mode ovfadj boost[1-0] dcckps3-0 table 20. keyboard sfrs mnemonicaddname 76543210 kbf (1) 9eh keyboard flag register kbe7 - 0 kbe (1) 9dh keyboard input enable register kbf7 - 0 kbls (1) 9ch keyboard level selector register kbls7 - 0 table 21. spi sfrs mnemonicaddname 76543210 spcon (1) c3h serial peripheral control spr2 spen ssdis mstr cpol cpha spr1 spr0 spsta (1) c4h serial peripheral status- control spif wcol modf spdat (1) c5h serial peripheral data r7 - 0 table 22. usb sfrs mnemonicaddname 76543210 usbcon bch usb global control usbe suspclk sdrmwup detach uprsm rmwupe confg fadden usbaddr c6h usb address fen uadd6-0 usbint bdh usb global interrupt wupcpu eorint sofint spint usbien beh usb global interrupt enable ewupcpu eeorint esofint espint uepnum c7h usb endpoint number epnum3-0 uepconx d4h usb endpoint x control epen n akien nakout nakin dtgl epdir eptype1 eptype0 uepstax ceh usb endpoint x status dir rxoutb1 stallrq txrdy stl/crc rxsetup rxoutb0 txcmp ueprst d5h usb endpoint reset ep6rst ep5rst ep4rst ep3rst ep2rst ep1rst ep0rst uepint f8h usb endpoint interrupt ep6int ep5int ep4int ep3int ep2int ep1int ep0int
40 at8xc5122/23 4202d?scr?06/05 note: 1. only for at8xc5122 uepien c2h usb endpoint interrupt enable ep6inte ep5inte ep4inte ep3inte ep2inte ep1inte ep0inte uepdatx cfh usb endpoint x fifo data fdat7 - 0 ubyctx e2h usb byte counter low (epx) byct6-0 ufnuml bah usb frame number low fnum7 - 0 ufnumh bbh usb frame number high crcok crcerr fnum10-8 table 22. usb sfrs mnemonicaddname 76543210 table 23. led sfrs mnemonicaddname 76543210 ledcon0 f1h led control 0 led3 led2 led1 led0 ledcon1 (1) e1h led control 1 led6 led5 led4
41 at8xc5122/23 4202d?scr?06/05 clock controller the clock controller is ba sed on an on-chip oscillato r feeding an on-chip phase lock loop (pll). all the internal clocks to the cpu core and peripherals are generated by this controller. on-chip oscillator the on-chip oscillator is composed of a single-stage inverter and a parallel feedback resistor. the xtal1 and xtal2 pins are resp ectively the input and the output of the inverter, which can be configured with off-chip components as a pierce oscillator (see figure 16). the on-chip oscillator has been designed and optimized to wo rk with an external 8 mhz crystal and very few load capacitance. then external load capacitors are not needed given that : ? the internal capacitance of the microcontroller and the stray capacitance of circuit board are enough to ensure a stable oscillation ? a very high accuracy on the os cillation frequenc y is not needed the circuit works on its fundamental frequency at 8 mhz. figure 16. oscillator schematic c1 and c2 represents the internal capacit ance of the microcontroller and the stray capacitance of the circuit board. it is re commended to implement the crystal as close as possible from the microcontroller package. quartz specification the equivalent circuit of a crystal is represented on the figure below : the equivalent serial resistance r1 must be lower than 100 ohm. feedback resistor xtal1 xtal2 8 mhz gnd gnd microcontroller c1 c2 to internal clock circuitry l1 c1 r1 c0
42 at8xc5122/23 4202d?scr?06/05 phase lock loop (pll) pll description the at8xc5122/23?s pll is used to generat e internal high frequency clock synchro- nized with an external low-frequency. figure 17 shows the internal structure of the pll. the pfld block is the phase frequency co mparator and lock detector. this block makes the comparison between the reference clock coming from the n divider and the reverse clock coming from the r divider and generates some pulses on the up or down signal depending on the edge position of the re verse clock. the pllen bit in pllcon register is used to enable the clock gener ation. when the pll is locked, the bit plock in pllcon register is set. the chp block is the charge pump that ge nerates the voltage reference for the vco by injecting or extracting charges from the external filter connected on pllf pin (see figure 18). value of the filter components are detailed in the section ?dc characteristics?. the vco block is the voltage controlled oscillator cont rolled by the voltage v ref pro- duced by the charge pump. it generates a square wave signal: the pll clock. the ck_pll frequency is define d by the follwing formula: f ck_pll = f ck_xtal1 * (r+1) / (n+1) figure 17. pll block diagram and symbol figure 18. pll filter value pll programming the pll must be programmed to work at 96 mhz frequency by means of pllcon and plldiv registers. as soon as the pll is enabl ed, the firmware must wait for the lock bit status to ensure that the pll is ready. pllen pllcon.1 n3:0 n divider r divider vco ck_pll ck_xtal1 pfld plock pllcon.0 pllf chp v ref up down r3:0 vss pllf vss 1,8 k ? 150 pf 33 pf
43 at8xc5122/23 4202d?scr?06/05 figure 19. pll programming flow clock tree architecture the clock controller outputs several different clocks as shown in figure 20: ? a clock for the cpu core ? a clock for the peripherals which is us ed to generate the timers, watchdog, spi, uart, and ports sampling clocks. this divided clock will be used to generate the alternate card clock. ? a clock for the usb ? a clock for the scib controller ? a clock for the dc/dc converter these clocks are enabled or not depending on the power reduction mode as detailed in section ?power management?, page 180. these clocks are generated using four pr esacalers defined in the table below: pll programming configure dividers n3:0= xxxxb r3:0= xxxxb enable pll pllen= 1 pll locked? plock= 1? prescaler register reload factor function pr1 ckrl ckrl[0:3] cpu & peripheral clocks pr2 sciclk sciclk[0:5] smart card pr3 scsr altkps[0:1] alternate card pr4 dcckps dcckps[3:0] dc/dc
44 at8xc5122/23 4202d?scr?06/05 figure 20. clock tree diagram cpu and peripheral clocks two clocks sources are available for cpu and peripherals: ? on-chip oscillator ? a derivative of the pll clock. these clock sources are configured by the pr1 prescaler to generate the cpu core ck_cpu and the peripheral clocks: ? ck_idle for alternate card and peripherals registers access ? ck_t0 for timer 0 ? ck_t1 for timer 1 ? ck_si for the uart ? ck_wd for the watchdog timer ? ck_spi for spi alternate card xtal1 xtal2 pd pcon.1 96 mhz ext48 pllcon.2 0 1 0 1 cks cksel.0 0 1 x2 ckcon0.0 pr1 ckrl[3:0] idl pcon.0 dc/dc pr4 pr2 ck_idle pr3 converter 1/2 ck_usb 0 1 ck_iso ck_cpu ck_xtal1 ck_pll dcckps[3:0] sciclk[5:0] scsr[3:2] 1 0 periphx2 ckcon0.x or 1 0 x2 ckcon0.0 ck_t0 peripherals ck_t1 ck_si ck_wd ck_spi ck_periph ck_idle ck_idle pllen pllcon.1 ck_xtal1 ck_pll ck_pll ck_xtal1 ck_xtal1 periph = t0, t1, si, wd or spi ckcon1.0 xtscs sciclk.7 cpu scib usb pll ck_dcdc 1/2 sciclk[5:0] =48 <48
45 at8xc5122/23 4202d?scr?06/05 the cpu and peripherals clocks frequenc ies are defined in the table below. x1 and x2 modes use of on-chip oscillator when the cpu and peripherals clocks are fe d by the on-chip oscillator, the cpu and peripherals can be configured independently in x1 or x2 mode depending on the fre- quencies wanted by the user. there is howev er one exception : the periperals can be configured in x2 mode while the cpu remains in x1 mode. this exception is handled by the hardware and the user does not need to take care of. the x1 or x2 modes can be individually selected for the cpu and each peripheral by means of ckcon0 and ckcon1 registers. at reset, the cpu and peripherals are set all by default to x1 mode. in this mode, changing any peripheral to x2 mode has no effect. when x2 bit is set in ckcon0 register, cpu and all peripherals are automati- cally switched to x2 mode. it is then possible for the user to individually switch any peripheral back to x1 mode. in x1 mode (x2 bit cleared in ckcon0 regsiter ), the pr1 prescaler is active while it is bypassed in x2 mode (x2 bit set in ckcon0 register). the x1 mode is true only when the prescaler pr1 is set to 1/2 (default condition at reset). cks x2 f ck_idle 00f ck_xtal1 /(2*(16-ckrl)) 01f ck_xtal1 10f ck_pll /(2*(16-ckrl)) 1 1 not allowed table 1. x1 and x2 mode selection cpu peripherals status frequenci x1 mode x1 mode allowed (default configuration at reset) f ck_idle = f ck_periph x1 mode x2 mode not allowed by the hardware x2 mode x1 mode allowed once the cpu is switched to x2 mode, the user is free to switch any of the peripherals to x1 mode f ck_idle = 2*f ck_periph x2 mode x2 mode allowed default configuration when cpu is switched to x2 mode f ck_idle = f ck_periph
46 at8xc5122/23 4202d?scr?06/05 figure 21. x1 mode when the x1 mode is selected, the cpu and peripherals work at 8mhz / x1 figure 22. x2 mode when the x2 mode is selected, the cpu works at 8 mhz / x2. the peripherals can work at 8 mhz / x2 or 8 mhz / x1. when the pr1 prescaler is different from 1/2, the usual x1 mode can not be defined. in this case, it is necessary to define a x1 or x2 equivalent mode from equivalent clock circuits. example : pr1=1/8, x2=0. in this configuration, the cpu works at 1 mhz. this frequency could also be obtained by an equivalent clock circ uit where the on-chip oscillator would run at 2 mhz in x1 mode or at 1 mhz in x2 mode. so we can say that the cpu works at 2 mhz / x1 or 1mhz / x2. as the x2 bit is cleared in ckcon0 register, we have f ck_idle = f ck_periph . 8 mhz 1/2 pr1 prescaler cpu frequency 4 mhz 4 mhz peripheral frequency crystal 8 mhz cpu frequency (x2 mode) 8 mhz 8 mhz peripheral frequency (x2 mode) 4 mhz 1/2 peripheral frequency (x1 mode) internal prescaler crystal
47 at8xc5122/23 4202d?scr?06/05 use of pll clock when the cpu clock is fed by the pll, th e x2 mode is forbidden. the bit x2 must always remain cleared in ckcon0 register. as the pr1 prescaler is always different from 1/2, the usual x1 mode can not be defined . so it is necessary to define an equiva- lent x1 or x2 mode from equivalent cl ock circuits, as in previous section. example: pr1=1/4, pll feeds the cpu. the cpu works in this case at 24 mhz. this frequency could also be obtained by an equi valent clock circuit where the on-chip oscil- lator would run at 48 mhz in x1 mode or at 24 mhz in x2 mode. so we can say that in this configuration, the cpu works at 48 mhz / x1 or 24 mhz / x2 (see figures below). as the x2 bit is cleared in ckco n0 register, we have always f ck_idle = f ck_periph . 8 mhz cpu frequency 1 mhz 1/8 pr1 prescaler (equivalent to) 2 mhz 1/2 external clock x1 mode selected periph frequency 1 mhz cpu frequency 1 mhz periph frequency 1 mhz (equivalent to) 1 mhz x2 mode selected cpu frequency 1 mhz periph frequency 1 mhz crystal external clock
48 at8xc5122/23 4202d?scr?06/05 scib clock the smart card interface block (scib) uses two clocks : ? the first one, ck_idle, is the peripheral clock used for the interface with the microcontroller. ? the second one, ck_iso, is inde pendant from the cpu clock and is generated from the pll or xtal1 output. pr2, a 6-bit prescaler, will be used to generate: 12/9.6/8/6.85/6/5.33/4.8/4.3 6/ ..../1mhz frequencies. scib clock frequency must be lower than cpu clock frequency. during scib reset, the ck_iso input must be in the range 1 - 5 mhz according to iso 7816. the scib clocks frequency is defined in figure 42 on page 74 and table 42 on page 74. two conditions must be met fo r a correct use of the scib: ? ck_cpu > 4/3 * ck_iso and ? ck_cpu < 6 * ck_iso. 96 mhz cpu frequency 24 mhz pll 1/4 prescaler 48 mhz 1/2 external clock cpu frequency 24 mhz (equivalent to) x1 mode selected 24 mhz cpu frequency 24 mhz (equivalent to) x2 mode selected periph frequency 24 mhz periph frequency 24 mhz periph frequency 24 mhz external clock
49 at8xc5122/23 4202d?scr?06/05 if the ck_cpu <= 4/3 * ck_iso, the scib doesn?t work. if the ck_cpu >= 6* ck_iso, the prog rammer must take care in three cases: ? read (or write) operation on a scib register followed immediatly with an other read (or write) operation on the same register. ? read (or write) operation on a scib register followed immediatly with an other read (or write) operation on a linked register. th e list of linked registers is in the table below. ? write operation on a register of the list below followed immediatly with a read operation on a scib register. to avoid any trouble, a delay must be added between the two accesses on the scib register. the scib must complete the first re ad (or write) operation before to receive the second. a solution is to add nop (no operation) instructions. the number of nop to add depends of the rate between ck_cpu and ck_iso (see table below). alternate card clock the alternate card uses the peripheral clock divided by the pr3 prescaler. (1; 1/2; 1/4; 1/8 division ratio). see section "alternate card ", page 78 for the definition of the alter- nate clock. dc/dc converter clock the dc/dc block needs a clock with a 50% duty cycle. the frequency must also be included in the range 3.68 mhz and 6 mhz. the pr4 prescaler is used to configure the dc/dc frequency. linked registers write in scicr and after read of scetu0-1 write in scibuf and after read of scisr wait after write operation on this registers scicr, scier, scetu0-1,scgt0-1, scwt0-3,sccon min clk_cpu max clk_cpu number of cpu cycles to add clk_cpu >= 6 * clk_iso clk_cpu <= 12 * clk_iso 6 ( example1 nop) clk_cpu >= 12* clk_iso clk_cpu <= 16 * clk_iso 12 ( example 2 nop) xtal1 (mhz) dcckps3:0 value prescaler factor dc/dc converter clk (mhz) 80 2 4
50 at8xc5122/23 4202d?scr?06/05 usb interface clock the usb interface uses two clocks : ? the first one is the cpu clock used for the interface with the microcontroller, ck_idle. ? the second one is the ck_usb supplied from the pll through a divider by 2. registers reset value = xxxx xxx0b reset value = xxxx 1111b table 24. clock selection regist er - cksel (s:85h) 76543210 -------cks bit number bit mnemonic description 7:1 - reserved the value read from this bit is i ndeterminate. do not set this bit. 0cks cpu oscillator select bit set this bit to connect cpu and peripherals to pll output. clear this to to connect cpu and peripherals to xtal1 clock input. table 25. clock reload register - ckrl (s:97h) 76543210 - - - - ckrl3 ckrl2 ckrl1 ckrl0 bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is i ndeterminate. do not set this bit. 3:0 ckrl3:0 clock reload register prescaler1 value f ck_cpu =[ 1 / 2*(16-ckrl)] * f ck_xtal1
51 at8xc5122/23 4202d?scr?06/05 reset value = x0x0 x000b table 26. clock configuration regist er 0 - ckcon0 (s:8fh) 76543210 - wdx2 - six2 - t1x2 t0x2 x2 bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6wdx2 watchdog clock this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4six2 enhanced uart clock (mode 0 and 2) this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 3- reserved the value read from this bit is i ndeterminate. do not set this bit. 2t1x2 timer 1 clock this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 1t0x2 timer 0 clock this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 0x2 system clock control bit cleared to select the pr1 output for cpu and all the peripherals . set to bypass the pr1 prescaler and to enable the individual peripherals ?x2? bits.
52 at8xc5122/23 4202d?scr?06/05 reset value = xxxx xxx0b reset value = 0000 0000b reset value = 0000 0000b table 27. clock configuration register 1 - ck con1 (s:afh) only for at8xc5122 76543210 -------spix2 bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is i ndeterminate. do not set this bit. 3- reserved the value read from this bit is i ndeterminate. do not set this bit. 0 spix2 spi clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. table 28. pll control register - pllcon (s:a3h) 76543210 - - - - - ext48 pllen plock bit number bit mnemonic description 7 - 3 - reserved the value read from these bits is always 0. do not set this bits. 2ext48 external 48 mhz enable bit set this bit to select xtal1 as usb clock. clear this bit to sele ct pll as usb clock. scib clock is controlled by ext48 bit and xtscs bit. 1 pllen pll enable bit set to enable the pll. clear to disable the pll. 0plock pll lock indicator set by hardware when pll is locked clear by hardware when pll is unlocked table 29. pll divider register - plldiv (s:a4h) 76543210 r3 r2 r1 r0 n3 n2 n1 n0 bit number bit mnemonic description 7 - 4 r3:0 pll r divider bits 3 - 0 n3:0 pll n divider bits
53 at8xc5122/23 4202d?scr?06/05 i/o port definition ports vs packages table 30. i/o number vs packages port 0 port 0 has the following functions: ? default function: port 0 is an 8-bit i/o port. ? alternate function: port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pu ll-ups when emitting 1?s and it can drive cmos inputs without external pull-ups. port 0 has the following configurations: ? default configuration: open drain bi-direc tional i/o port. port 0 pins that have 1?s written to them float, and in this state they can be used as high- impedance inputs. ? configuration 2: low speed output, ?kb_out? ? configuration 3: push-pull output p0 p1 p2 p3 p4 p5 total vqfp64 qfn64 88886846 vqfp32 qfn32 -8-8-117 plcc28 - 6 - 6 - 1 13
54 at8xc5122/23 4202d?scr?06/05 port 1 port 1 has the following functions: ? default function : only port 1.2, p1.6 and p1.7 are standard i/o?s; the other ports can be activated only with the scib function. ? alternate function and configuration: see table 31. table 31. port 1 description. port 2 port 2 has the following functions: ? default function: port 2 is an 8-bit i/o port. ? alternate function 1: port 2 is also the multiplexed high-order address during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1?s and it can drive cmos inputs without external pull-ups. port 2 has the following configurations: ? default configuration: pseudo bi-directi onal ?port51? digital input/output with internal pull-ups. ? configuration 1: push-pull output ? configuration 2: low speed output, ?kb_out ? configuration 3: input with weak pull-up, ?wpu input? port alternate function configuration signal description mode comments cio smart card interface function card i/o quasi-bidirectional port supplied by dc/dc converter low level at reset. caution : if dpu bit is set in auxr register, the weak-pull of the port is disabled cc8 smart card interface function card contact 8 quasi-bidirectional port supplied by dc/dc converter low level at reset caution : if dpu bit is set in auxr register, the weak-pull of the port is disabled p1.2 cpres smart card interface function card presence quasi-bidirectional po rt supplied by vcc weak & medium pull-up?s can be disconnected by cpresres bit in pmod0 regsiter high level at reset cc4 smart card interface function card contact 4 quasi-bidirectional port supplied by dc/dc converter low level at reset caution : if dpu bit is set in auxr register, the weak-pull of the port is disabled cclk smart card interface function card clock push-pull port supplied by dc/dc converter low level at reset crst smart card interface function card reset push-pull port supplied by dc/dc converter low level at reset p1.6 ss ss pin of the spi function quasi- bidirectional supplied by vcc p1.7 cclk1 alternate card clock output quasi-bidirectional supplied by vcc alt ernate card clock function disabled quasi-bidirectional supplied by vcc alternate smart card clock enabled switched automatically to push-pull (see table 47 on page 82 )
55 at8xc5122/23 4202d?scr?06/05 port 3 port 3 has the following functions: ? default function: port 3 is an 8-bit i/o port. ? alternate functions: see table below port 3 has the following configurations: ? default configuration: pseudo bi-directi onal ?port51? digital input/output with internal pull-ups. ? alternate configurations: see table 32. table 32. port 3 description port alternate functions configurations signal description mode 1 mode 2 mode 3 mode 4 p3.0 rxd receiver data input (asynchronous) or data input/output (synchronous) of the serial interface push-pull kb_out input wpu p3.1 txd transmitter data output (asynchronous) or clock output (synchronous) of the serial interface push-pull kb_out input wpu p3.2 int0 external interrupt 0 i nput/timer 0 gate control input led0 p3.3 int1 external interrupt 1input/timer 1 gat e control input push-pull kb_out input wpu p3.4 t0 timer 0 counter input push-pull kb_out input wpu led1 p3.5 t1 timer 1 counter input p3.6 wr external data memory write strobe; latches the data byte from port 0 into the external data memory led2 p3.7 rd external data memory read strobe; enables the external data memory. port 3 can drive cmos inputs without external pull-ups led3
56 at8xc5122/23 4202d?scr?06/05 port 4 port 4 has the following functions: ? default function: port 4 is an 6-bit i/o port. ? alternate functions: see table below port 4 has the following configurations: ? default configuration: pseudo bi-directi onal ?port51? digital input/output with internal pull-ups. ? alternate configurations: see table 33. table 33. port 4 description port 5 port 5 has the following functions: ? default function: port 5 is an 8-bit i/o port. ? alternate function 1: port 5 is an 8-bit keyboard port kb0 to kb7. port 5 has the following configurations: ? default configuration: pseudo bi-directi onal ?port51? digital input/output with internal pull-ups. ? alternate configuration: see table 34. table 34. port 5 description port alternate functions configurations signal description mode 1 mode 2 mode 3 p4.0 miso spi master in slave out i/o p4.1 mosi spi master out slave in i/o p4.2 sck spi clock p4.3 push-pull kb_out input mpu p4.4 push-pull kb_out input mpu p4.5 push-pull kb_out input mpu port configurations mode 1 mode 2 mode 3 comments p5.0 push-pull input mpu input wpu first cluster p5.1 push-pull input mpu input wpu p5.2 push-pull input mpu input wpu p5.3 push-pull input wpd input wpu second cluster p5.4 push-pull input wpd input wpu p5.5 push-pull input wpd input wpu p5.6 push-pull input wpd input wpu third cluster p5.7 push-pull input wpd input wpu
57 at8xc5122/23 4202d?scr?06/05 port configuration standard i/o p0 the p0 port is described in figure 23. figure 23. standard input/output port quasi bi-directional port the default port output configuration for st andard i/o ports is the quasi-bi-directional output that is common on the 80c51 and most of its derivatives. the ?port51? output type can be used as both an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the port outputs a logic low state, it is driven strongly and is able to sink a fairly large current. these features are somewhat similar to an ope n-drain output except that there are three pull-up transistors in the quasi-bi-direction al output that serve different purposes. one of these pull-ups, called the weak pull-up, is turned on whenever the port latch for the pin contains a logic 1. the weak pull-up sources a very small cu rrent that will pull the pin high if it is left floating. the weak pul l-up can be turned off by the dpu bit in auxr register. a second pull-up, called the medium pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the pri- mary source current for a quasi-bi-directional pi n that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only the weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the medium pull-up and take the voltage on the port pin below its input threshold. note: for cio, cc4, cc8 ports of scib interface , in input mode when the icc (smart card) is driving the port pin : ? if 0 < vin < cvcc/2 : weak pu ll-up is active (~100kohm) ? if cvcc/2 < vin < cvcc : weak (~100kohm) and medium (~12kohm) pull- up?s are active mux pin addr/data control vcc 1 0 input data port latch data pmos nmos vss
58 at8xc5122/23 4202d?scr?06/05 the ?port51? is described in figure 24. figure 24. quasi bi-directional port push-pull output configuration the push-pull output configuration has the same pull-down struct ure as both the open drain and the quasi-bi-directional output modes, but provides a continuous strong pull- up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port configuration is shown in figure 25. figure 25. push-pull output input with medium or weak pull-up configuration the input with pull-up (input mpu and input wp u) configuration is shown in figure 26. 2 cpu input pin strong weak medium n p p p clock delay port latch data data dpu (auxr.7) vss vcc vcc vcc pin strong n p port latch data pmos nmos
59 at8xc5122/23 4202d?scr?06/05 figure 26. input with pull-up input with weak pull-down configuration the input with pull-down (input wpd) configuration is shown in figure 27 figure 27. input with pull-down low speed output configuration the low speed output with low speed t fall and t rise can drive keyboard. the current limitation of the led2ctrl block requires a polarisation current of about 250 a. this block is automatically disabled in power-down mode. the low speed output configuration (kb_out) is shown in figure 28. figure 28. low-speed output led source current the led configuration is shown in figure 29. input pin data weak p medium p stuck to 0 if medium stuck to 0 if weak input pin data weak n 1 pin p pweakctrl port latch data n n nmos pcon.1 weak led2ctrl
60 at8xc5122/23 4202d?scr?06/05 figure 29. led source current notes: 1. when switching a low level, ledctrl device has a permanent current of about n ma/15 (n is 2, 4 or 8). 2. the port must be configured as standard c51 port by means of pmod0 and pmod1 registers and the level of current must be programmed by means of ledcon0 and ledcon1 registers before switching the led on. table 35. led source current ledx.1 ledx.0 port latch data nmos pin comments 00 0 10 led control disabled 00 1 01 01 0 00 led mode 2 ma 01 1 01 10 0 00 led mode 4 ma 10 1 01 11 0 00 led mode 10 ma 11 1 01 pin port latch data ledx.0 ledx.1 nmos n n ledctrl
61 at8xc5122/23 4202d?scr?06/05 registers reset value = 0000 0x00b reset value = 00xx 0xxxb table 36. port mode register 0 - pmod0 (91h) for at8xc5122 7654 3 210 p3c1 p3c0 p2c1 p2c0 cpresres - p0c1 p0c0 bit number bit mnemonic description 7 - 6 p3c1-p3c0 port 3 configuration bits (applicable to p3.0, p3.1, p3.3, p3.4 only) 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with weak pull-up 5-4 p2c1-p2c0 port 2 configuration bits 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with weak pull-down 3 cpresres card presence pull-up resistor cleared to connect the internal 100k pull-up set to disconnect the internal pull-up 2- reserved the value read from this bit is in determinate. do not set this bit. 1-0 p0c1-p0c0 port 0 configuration bits 00 c51 standard p0 01 reserved 10 output low speed 11 push-pull table 37. port mode register 0 - pmod0 (91h) for at83c5123 7654 3 210 p3c1 p3c0 - - cpresres - - - bit number bit mnemonic description 7 - 6 p3c1-p3c0 port 3 configuration bits (applicable to p3.0, p3.1, p3.3, p3.4 only) 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with weak pull-up 5-4 reserved the value read from these bits are indeterminate. do not set these bit. 3 cpresres card presence pull-up resistor cleared to connect the internal 100k pull-up set to disconnect the internal pull-up 2-0 - reserved the value read from these bits are indeterminate. do not set these bit.
62 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b reset value = xxxx 00xxb table 38. port mode register 1 - pmod1 (84h) for at8xc5122 76543210 p5hc1 p5hc0 p5mc1 p5mc0 p5lc1 p5lc0 p4c1 p4c0 bit number bit mnemonic description 7 - 6 p5hc1-p5hc0 port 5 high configuration bits (applicable from p5.6 to p5.7 only) 00 quasi bi-directional 01 push-pull 10 input with weak pull-down 11 input with weak pull-up 5 - 4 p5mc1-p5mc0 port 5 medium configuration bits (applicable from p5.3 to p5.5 only) 00 quasi bi-directional 01 push-pull 10 input with weak pull-down 11 input with weak pull-up 3 - 2 p5lc1-p5lc0 port 5 low configuration bits (applicable from p5.0 to p5.2 only) 00 quasi bi-directional 01 push-pull 10 input with medium pull-up 11 input with weak pull-up 1 - 0 p4c1-p4c0 port 4 configuration bits (applicable from p4.3 to p4.5 only) 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with medium pull-up table 39. port mode register 1 - pmod1 (84h) for at83c5123 76543210 - - - - p5lc1 p5lc0 - - bit number bit mnemonic description 7 - 4 reserved the value read from this bit is i ndeterminate. do not set this bit. 3 - 2 p5lc1-p5lc0 port 5 low configuration bits (applicable from p5.0 to p5.2 only) 00 quasi bi-directional 01 push-pull 10 input with medium pull-up 11 input with weak pull-up 1 - 0 reserved the value read from this bit is i ndeterminate. do not set this bit.
63 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b reset value = 0000 0000b table 40. led port control register 0 - ledcon0 (f1h) 76543210 led3.1 led3.0 led2.1 led2.0 led1.1 led1.0 led0.1 led0.0 bit number bit mnemonic description 7 - 6 led3 port led3 configuration bits 00 led control disabled 01 2 ma current source when p3.7 is c onfigured as quasi-bi-directional mode 10 4 ma current source when p3.7 is configured as quasi- bi-directional mode 11 10 ma current source when p3.7 is configured as quasi-bidirect. mode 5 - 4 led2 port led2 configuration bits 00 led control disabled 01 2 ma current source when p3.6 is c onfigured as quasi-bi-directional mode 10 4 ma current source when p3.6 is configured as quasi- bi-directional mode 11 10 ma current source when p3.6 is configured as quasi-bidirect. mode 3 - 2 led1 port led1 configuration bits 00 led control disabled 01 2 ma current source when p3.4 is c onfigured as quasi-bi-directional mode 10 4 ma current source when p3.4 is configured as quasi- bi-directional mode 11 10 ma current source when p3.4 is configured as quasi-bidirect. mode 1 - 0 led0 port led0 configuration bits 00 led control disabled 01 2 ma current source when p3.2 is c onfigured as quasi-bi-directional mode 10 4 ma current source when p3.2 is configured as quasi- bi-directional mode 11 10 ma current source when p3.2 is configured as quasi-bidirect. mode table 41. led port control register 1- ledcon1 (f1h) only for at8xc5122 76543210 - - led6.1 led6.0 led5.1 led5.0 led4.1 led4.0 bit number bit mnemonic description 7 - 6 reserved the value read from this bit is in determinate. do not set this bit. 5 - 4 led6 port led6 configuration bits 00 led control disabled 01 2 ma current source when p4.5 is c onfigured as quasi-bi-directional mode 10 4 ma current source when p4.5 is configured as quasi- bi-directional mode 11 10 ma current source when p4.5 is configured as quasi-bidirect. mode 3 - 2 led5 port led5 configuration bits 00 led control disabled 01 2 ma current source when p4.4 is c onfigured as quasi-bi-directional mode 10 4 ma current source when p4.4 is configured as quasi- bi-directional mode 11 10 ma current source when p4.4 is configured as quasi-bidirect. mode 1 - 0 led4 port led0 configuration bits 00 led control disabled 01 2 ma current source when p4.3 is c onfigured as quasi-bi-directional mode 10 4 ma current source when p4.3 is configured as quasi- bi-directional mode 11 10 ma current source when p4.3 is configured as quasi-bidirect. mode
64 at8xc5122/23 4202d?scr?06/05 smart card interface block (scib) the scib provides all signals to interface directly with a smart card. the compliance with the iso7816, emv?2000, gsm and whql standards has been certified. both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro- cessor card) are supported. the component supplies the different voltages requested by the smart card. the power off sequence is directly managed by the scib. the card presence switch of the smart card connector is used to detect card insertion or card removal. in case of card removal, th e scib de-activates the smart card using the de-activation sequence. an interrupt can be generated when a card is inserted or removed. any malfunction is reported to the microc ontroller (interrupt + control register). the different operating modes are configured by internal registers. ? support of iso/iec 7816 ? character mode ? one transmit/receive buffer ? 11 bits etu counter ? 9 bits guard time counter ? 32 bits waiting time counter ? auto character repetition on error signal detection in transmit mode ? auto error signal generation on parity error detection in receive mode ? power on and power off sequence generation ? manual mode to drive directly the card i/o
65 at8xc5122/23 4202d?scr?06/05 block diagram the smart card interface block diagram is shown figure 30: figure 30. scib block diagram definitions this paragraph introduces some of the terms used in iso 7816-3 and emv recommen- dations. please refer to the full recommendations for a complete list of terms. terminal and icc terminal is the reader, icc is the integrated circuit card etu elementary timing unit (bit time) t=0 character oriented half duplex protocol t=0 t=1 block oriented half duplex protocol t=1 activation: cold reset reset initiated by the terminal with vcc pow er-up. the card will answer with atr (see below) activation: warm reset reset initiated by the terminal with vcc already powered-up, and after a prior atr or warm reset de-activation deactivation by the terminal as a result of : unresponsive icc, or icc removal. barrel shifter scart fsm interrupt generator power on power off fsm i/o mux io (in) io (out) clk rst c4 (out) clk_iso c8 (out) c4 (in) c8 (in) waiting time counter guard time counter vcard int clk_cpu etu counter sci registers
66 at8xc5122/23 4202d?scr?06/05 atr answer to reset. response from the ic c to a reset initiated by the terminal f and d f = clock rate conversion fact or, d = bit rate adjustment factor. etu is defined as : etu = f/(d*f) with f = card clock frequency. if f is in hertz, etu is in second. f and d are available in the atr (byte ta1). the default values are f=372, d=1. guard time the time between 2 leading edges of the start bit of 2 consecutive characters is com- prised of the character durati on (10) plus the guard time. be aware that the guard time counter and the guard time registers in the at8xc5122/23 consider the time between 2 consecutive characters. so the equation is guard time c ounter = guard time + 10. in other words, the guard time is the number of stop bits between 2 characters sent in the same direction. extra guard time iso iec 7816-3 and emv introduce the extra guard time to be added to the minimum guard time. extra guard time only apply to c onsecutive characters sent by the termi- nal to the icc. the tc1 byte in the atr define the number n. for n=0 the character to character duration is 12 etus. for n=254 the character to character duration is 266. for n=255 (special case) the minimum character to character duration is to be used : 12 for t=0 protocol and 11 for t=1 protocol. block guard time the time between the leading edges of 2 cons ecutive characters sent in opposit direc- tion. iso iec 7816-3 and emv recommend a fixed block guard time of 22 etus. work waiting time (wwt) in t=0 protocol wwt is the interval between the leading edge of any character sent by the icc, and the leading edge of the previous character sent either by the icc or the terminal. if no character is received by the terminal after wwt max time, the terminal initiates a de-activation sequence. character waiting time (cwt) in t=1 protocol cwt is the interval between the leading edge of 2 consecutive charac- ters sent by the icc. if the next characte r is not received by the terminal after cwtmax time, the terminal initiate s a de-activation sequence. block waiting time (bwt) in t=1 protocol bwt is the interval betw een the leading edge of the start bit of the last character sent by the terminal that gives the right to sent to the icc, and the leading edge of the start bit of the first character sent by the icc. if the first character from the icc is not received by the terminal after bwtmax time, the termina l initiates a de-acti- vation sequence. waiting time extention (wtx) in t=1 protocol the icc ca n request a waiting time ex tension with a s(wtx request) request. the terminal should acknowlege it. the waiting time between the leading edge of the start bit of the last character sent by the terminal that gives the right to sent to the icc, and the leading edge of the start bit of the firs t character sent by the icc will be bwt*wtx etus. parity error in t=0 protocol in t=0 protocol, a terminal (respectively an icc) detecting a parity error while receiving a character shall force the card io line at 0 st arting at 10.5 etus, thus reducing the first guard bit by half the time. the terminal (res pectively an icc) shall maintain a 0 for 1 etu min and 2 etus max (according to iso iec) or to 2 etus (according to emv). the icc (respectively a terminal) shall monitor the card io to detect this error signal then attempt to repeat the characte r. according to emv, following a parity error the character can be repeated one time, if parity error is detected again this procedure can be repeated 3 more times. the same character can be transmitted 5 times in total. iso
67 at8xc5122/23 4202d?scr?06/05 iec7816-3 says this procedure is mandatory in atr for card supporting t=0 while emv says this procedure is mandatory for t=0 but does not apply for atr. functional description the architecture of the smart card interface block can be detailed as follows: barrel shifter the barrel shifter performs the translation between 1 bit serial data and 8 bits parallel data the barrel function is useful for character repetition si nce the character is still present in the shifter at the end of the character transmission. this shifter is able to shift the data in both directions and to invert the input or output value in order to manage both direct and inverse iso7816-3 convention. coupled with the barrel shifter is a parity checker and generator. there are 2 registers connected to this barr el shifter, one for the transmission and one for the reception. they act as buffers to relieve the cpu of timing constraints. scart fsm (smart card asynchronous receiver transmitter finite state machine) this is the core of the block. its purpose is to control the barrel shifter. to sequence cor- rectly the barrel shifter for a reception or a transmission, it uses t he signals issued by the different counters. one of the most importa nt counters is the guard time counter that gives time slots corresponding to the character frame. the scart fsm is enabled only in uart mode. the transition from the receip t mode to the transmit mode is done automatically. priority is given to the transmission. transmission refers to terminal transmission to the icc. reception refers to reception by the terminal from the icc. etu counter the etu (elementary timing unit) counter co ntrols the working frequency of the barrel shifter, in fact it generates the enable signal of the barrel shifter. it receives the card clock, and generates the etu clock. the card clock frequency is called ?f? below. the etu counter is 11 bit wide. a special compensation mode c an be activated. it accomo dates situations where the etu is not an integer number of card clock (ck_iso). the compensation mode is con- trolled by the comp bit in scetu1 regist er bit position 7. with comp=1 the etu of every character even bits is reduced by 1 ca rd clock period. as a result, the average etu is : etu_average = (etu - 0.5). one should bear in mind that the etu counter should be programmed to de liver a faster etu which will be reduced by the comp mechanism, not the other way around. this allo ws to reach the required precision of the character duration specified by the iso7816-3 standard. example1 : f=372, d=32 => etu= f/d = 11.625 clock cycles. we select etu[10-0] = 12 , comp=1. etuaverage= 12 - (0.5*comp) = 11.5 the result will be a full charac ter duration (10 bit) = (10 - 0.107)*etu. the emv specifi- cation is (10 +/- 0.2)*etu guard time counter the minimum time between the leading edge of the start bit of 2 consecutive characters transmitted by the terminal is controlled by the guard time c ounter, as described in figure 33.
68 at8xc5122/23 4202d?scr?06/05 the guard time counter is an 9 bit counter it is initialized at 001h at the start of a trans- mission by the terminal. it then increments itself at each etu until it reach the 9 bit value loaded into the scgt1[0] concatenated with scgt0[7:0]. at this time a new ter- minal transmission is enabled and the guar d time counter stop incrementing. as soon as a new transmission start, the guard time counter is re-initialized at 1 decimal value. it should be noted that the value of the guard time counter cannot be red. reading scgt1,0 only gives the minimum time betwe en 2 characters that the guard time counter will allow. care must be taken with the guard time counter which counts the duration between the leading edges of 2 consecutive characters. this correspond to the character dura- tion (10 etu) plus the guard time as defined by the iso and emv recommendations. to program guard time = 2 : 2 stop bits betwe en 2 characters which is equivalent to the minimum delay of 12 etus between the leadi ng edges of 2 consecutive characters, scgt1[0],scgt0[7:0] should be loaded with the value 12 decimal. see figure 31 figure 31. guard time. block guard time counter the block guard time counter provides a way to program a minimum time between the leading edge of the start bit of a character received from the icc and the leading edge of the start bit of a character sent by the terminal. iso iec 7816-3 and emv recommend a fixed block guard time of 22 etus. the at 8xc5122/23 offer the possibility to extend this delay up to 512 etus. the block guard time is a 9 bit counter. when the block guard time mode is enabled (bgten=1 in scsr register) the block guard time counter is initialized at 000h at the start of each character transmissions from the icc. it then increments at each etu until it reach the 9 bit value loaded into shadow scgt1, 0 registers, or until it is re-initialized by the start of an new transmission from the icc. if the block guard time counter reaches the 9 bit value loaded into shadow scgt1,0 registers, a transmission by the terminal is enabled, and the block guard time counter stop incrementing. the block guard time counter is re-initialized at the start of each terminal transmission. the scgt1 scgt0 shadow registers are loaded with the content of gt[8-0] contained in the registers scgt1[0),scgt0(7:0] with the rising edge of the bit bgten in the scsr register. see figure 33. char n+1 char n+2 char n+3 >= scgt transmission to icc
69 at8xc5122/23 4202d?scr?06/05 figure 32. block guard time. figure 33. guard time and block guard time counters to illustrate the use of guard time and block guard time, let us consider the iso/iec7816-3 recommendation : guard time = 2 (minimum delay between 2 consecu- tive characters sent by the terminal = 12 etus), and block guard time = 22 etus. after a smart card reset ? write 00decimal in scgt1, write 21decimal in scgt0 ? set bgten in scsr (bgten was 0 before as a result of the smart card reset) ? write 12decimal in scgt0 now the guard time and bloc k guard time are pr operly initialized. the terminal will insure a minimun 12 etus between 2 leadin g edges of 2 consecut ive characters trans- mitted. the terminal will also insure a minimum of 22 etus between the leading edge of a character sent by the icc, and th e leading edge of a character sent by the terminal. there is no need to write scgt1,0 again and again. waiting time (wt) counter the wt counter is a 32 bits down counter which can be loaded with the value contained in the scwt3, scwt2, scwt1, scwt0 regist ers. its main purpose is timeout signal generation. it is 32 bits wide and is decremented at the etu rate. see figure 34. char 1 char 2 char n char n+1 char n+2 char n+3 >= block guard time >= scgt reception from icc transmission to icc write ?block guard time? in scgt1,0 write scgt1,0 with and set bgten to transfer the value to the shadow scgt1,0 registers a value for guard time etu counter block guard time counter enable scgt1 scgt0 9 bits guard time counter gt[8:0] shadow scgt1 ,shadow scgt0 9 bits comparator transmit comparator 9 bits 9 bits enable transmit
70 at8xc5122/23 4202d?scr?06/05 when the wt counter times out, an interrupt is generated and the scib function is locked: reception and emission are disabled. it can be enabled by resetting the macro or reloading the counter. the waiting time counter can be used in t=0 protocol for the work waiting time. it can be used in t=1 protocol for the character wa iting time and for the block waiting time. see the detailed explanation below. figure 34. waiting time counter in the so called manuel mode, the counter is loaded, if wten = 0, during the write of scwt2 register. the counter is loaded with a 32 bit word built with scwt3 scwt2 scwt1 scwt0 registers (scwt0 contain wt [7-0] byte. wten is located in the scicr register. when wten=1 and in uart mode, the counter is re-loaded at the occurence of a start bit. this mode will be detailed below in t=0 protocol and t=1 protocol. in manual mode, the wten signal controls t he start of the counter (rising edge) and the stop of the counter (falling edge). after a timeout of the counter, a falling edge on wten, a reload of scwt2 and a rising edge of wten are necessary to start again the counter and to release the scib macro. the reload of scwt2 transfers all scwt0, scwt1, scwt2 and scwt3 registers to the wt counter. in uart mode there is an automatic load on the start bit detection. this automatic load is very useful for changing on-the-fly the timeout value since there is a register to hold the load value. this is the case for t=1 protocol. in t=0 protocol the maximun interval betw een the start leading edge of any character sent by the icc and the start of the previous character sent by either the icc or the ter- minal is the maximum work waiting time. the work waiting ti me shall not exceed 960*d*wi etus with d and wi parameters are returned by the field ta1 and tc2 respectively in the answer to reset (atr). th is is the value the user shall write in the scwt0,1,2,3 register. this value will be reloaded in the waiting time counter every start bit. etu counter wt counter timeout scwt2 scwt1 scwt0 wt[31:0] load wten start bit uart write_scwt2 scwt3
71 at8xc5122/23 4202d?scr?06/05 figure 35. t=0 mode in t=1 protocol : the maximum interval between the leading edge of the start bit of 2 consecutive characters sent by the icc is called maximum character waiting time. the character waiting time shall not exceed (2 **cwi + 11) etus with 0 =< bwi =< 5. con- sequently 12 etus =< cwt =< 43 etus. t=1 protocol also specify the maximum block waiting time. this is the time between the leading edge of the last character sent by the terminal giving the right to send to the icc, and the leading edge of the start bit of t he first character sent by the icc. the block waiting time shall not exceed (2**bw i*960 + 11) etus with 0 =< bwi =< 4. con- sequently 971 etus =< bwt =< 15371 etus. in t=1 protocol it is possi ble to extend the block waiti ng time with the waiting time extension (wtx). when selected the waiting time becomes bwt*wtx etus. the waiting time counter is 32 bit wi de to accomodate this feature. it is possible to take advantage of the auto matic reload of the waiting time counter with a start bit in uart mode (t=1 protocol use uart mode) . if the terminal sends a block of n characters, and the icc is supposed to respond immediately after, then the follow- ing sequence can be used. while sending the (n-1)th character of the block, the terminal can write the scwt0,1,2,3 with bwimax. at the start bit of the nth character, the bw imax is loaded in the waiting time counter during the transmission of the nth character, the terminal can write scwt0,1,2,3 with the cwimax. at the start bit of the first character sent by the icc, t he cwimax will be loaded in the waiting time counter. figure 36. t=1 mode char 1 char 2 < wt > gt bloc 1 char 1 char 2 char n bloc 2 char n+1 char n+2 char n+3 < bwt < cwt transmission reception
72 at8xc5122/23 4202d?scr?06/05 power-on and power-off fsm the power-on power-off finite state machine (fsm) applies the signals on the smart card in accordance with iso7816-3 standard. it conducts the activation (cold reset and warm reset as well as de-activation) it al so manages the exception conditions such as overcurrent (see dc/dc converter) to be able to power on the scib, the card pr esence is mandatory. upon detectection of a card presence, the terminal initiate a cold reset activation. the cold reset activation terminal procedure is as follow and the figure 37. timing indications are given according to iso iec 7816 ? reset= low , i/o in the receive state ? power vcc (see dc/dc converter) ? once vcc is established, apply clock at time ta ? maintain reset low until time ta+tb (tb< 400 clocks) ? monitor the i/o line for the answer to reset (atr) between 400 and 40000 clock cycles after tb. ( 400 clocks < tc < 40000clocks) figure 37. scib activation cold reset s equence after a card insertion the warm reset activation terminal procedure is as follow and the figure 38 ? vcc active, reset = high, clk active ? terminal drive reset low at time t to initiate the warm reset. reset=0 maintained for at least 400 clocks until time td = t+te (400 clocks < te) ? terminal keep the io line in receive state ? terminal drive reset high after at least 400 clocks at time td ? icc shall respond with an atr within 40000 clocks (tf<40000 clocks) figure 38. scib activation warm reset sequence cvcc crst cclk cio data undefined ta ta+tb tb+tc cvcc crst cclk cio data t td=t + te td + tf undefined
73 at8xc5122/23 4202d?scr?06/05 removal of the smart card will automatically start the power off sequence as described in figure 39. the scib deactivation sequence after a reset of the cpu or after a lost of power supply is iso7816-3 compliant. the switching order of the signals is the same as in figure 39 but the delay between signals is analog and not clock dependant. figure 39. scib deactivation sequence after a card extraction interrupt generator there are several sources of interruption but the scib macro-cell issues only one inter- rupt signal: scibit. figure 40. scib interrupt sources this signal is high level active . each of the sources is able to activate the scib interrup- tion which is cleared when the smart card interrupt register is read by the microcontroller. if during the read of the smart card interrupt register another inte rrupt occurs, the acti- vation of the corresponding bit in the smart card interrupt register and the new scib interruption is delayed until the interrupt register is read by the microcontroller. warning : each bit of the sciir register is irrelevant while the corresponding interrup- tion is disabled in scier register. when t he interruption mode is not used, the bits of the scisr register must be used instead of the bits of the sciir register. cvcc crst cclk cio 8 clock cycles esctbi icarder escwti escri escpi evcarder transmit buffer copied to shift register output current out of range output voltage out of range timeout on wt counter complete transmission complete reception parity error detected scib it escti sctbi icarderr vcarderr scwti scti scri scpi
74 at8xc5122/23 4202d?scr?06/05 additional features clock the ck_iso input must be in the range 1 - 5 mhz according to iso 7816. the ck_iso can be programmed up to 12 mhz. in this case, the timing specification of the output buffer will no t comply to iso 7816. figure 41. clock diagram of the scib block figure 42. prescaler 2 description the division factor sciclk must be smaller than 49. if it is greater or equal to 49, the pr2 prescaler is locked. see figure 17 clock tree diagram in the clock controller chapter. table 42. examples of clock settings card presence input the internal pull-up (weak pull-up) on card presence input can be disconnected in order to reduce the consumption (cpresres, bit 3 in pmod0). in this case, an external resistor (typically 1 m ? ) must be externally tied to vcc. cpres input can generate an interrupt (see interrupt system section). the detection level can be selected. pr2 ck_cpu ck_iso scib ck_pll or ck_idle ck_xtal1 pr2 1/(2*(48 - sciclk[5-0])) ck_iso ext48 pllcon.2 0 1 ck_pll ck_xtal1 xtscs sciclk.7 sciclk[5:0] <48 =48 xtal1 (mhz) ext48 sciclk ck_ iso 80 36 4 8 0 44 12 80 42 8 80 40 6 80 24 2 80 0 1
75 at8xc5122/23 4202d?scr?06/05 transmit / receive buffer the contents of the scibuf transmit / receive buffer is transferred or received into / from the shift register. the shif t register is not accessible by microcontroller. its role is to prepare the byte to be copied on the i/o pin for a transmissi on or in the scibuf buffer after a reception. during a character transmission process, as soon as the contents of the scibuf buffer is transferred to the shift register, the sctbe bit is set in scisr register to indicate that the scibuf buffer is empty and ready to a ccept a new byte. this mechanism avoids to wait for the complete transmission of the prev ious byte before writing a new byte in the buffer and enables to speed up the transmission. ? if the character repetition mode is no t selected (bit crep=0 in scicr), as soon as the contents of the shift regist er is transferred to i/o pin, the sctc bit is set in scisr register to indica te that the byte has been transmitted. ? if the character repetition mode is selected (bit crep= 1 in scicr) the terminal will be able to repeat characte rs as requested by the icc (see the parity error in t=0 protocol description in the definition paragraph above). the sctc bit in scisr regist er will be set after a successful transmission (no retry or no further retry requested by the icc). if the number of retries is ex hausted (up to 4 retries depending on crepsel bit in scsr) and the last retry is still unsu ccessful, the sctc bit in scisr will not be set and the scpe bit in scis r register will be set instead. during a character reception process, the conten ts of the shift regist er is transferred in the scibuf buffer. ? if the character repetition mode is no t selected (bit crep=0 in scicr), as soon as the contents of the shift register is transferred to the scibuf the scrc bit is set in scisr register to indicate that the byte has been received, and the scibuf contains a valid character ready to be red by the microcontroller. ? if the character repetition mode is selected (bit crep= 1 in scicr) the terminal will be able to r equest repetition if the received character exhibit a parity error. up to 4 retries c an be requested depend ing on crepsel bit in scsr. the scrc bit will be set in scisr register after a successful reception, first reception or after retr y(ies). if the number of retries is exhausted (up to 4 retrie s depending on crepsel bit in scsr) and the last retry is still unsuccessful, the scrc bit and the scpe bit in scisr register will be set. it will be possible to read the erro neous character. warning : the sctbi, scti scri and scpi bi ts have the same function as sctbe, sctc, scrc and scpe bits. the first ones ar e able to generate in terruptions if the interruptions are enabled in scier register wh ile the second ones are only status bits to be used in pulling mode. if the interruption m ode is not used, the st atus bits must be used. the sctbi, scti and scri bits do not contain valid information while their respective interrupt enable bits esctbi, excti, escri are cleared.
76 at8xc5122/23 4202d?scr?06/05 figure 43. charactertransmission diagram scibuf transmitted character shift register i/o pin sctbe sctc scisr register sctbi scti sciir register esctbi escti scier register parity error scpe scpi parity error
77 at8xc5122/23 4202d?scr?06/05 figure 44. character reception diagram scib reset the scicr register contains a reset bit. if se t, this bit generates a reset of the scib and its registers. table 43 define s the scib registers that are reset and their reset values. table 43. reset values for sci registers scibuf received character shift register i/o pin sctbe sctc scisr register scrc sctbi scti sciir register scri esctbi escti scier register escri scpe register name scib reset value (binary) scicr 0000 0000 sccon 0x00 0000 scisr 1000 0000 sciir 0x00 0000 scier 0x00 0000 scsr x000 1000 scibuf 0000 0000 scetu1, scetu0 xxxx x001, 0111 0100 (372) scgt1, scgt0 0000 0000, 0000 1100 (12) scwt3, scwt2, scwt1, scwt0 0000 0000, 0000 0000, 0010 0101, 1000 0000 (9600) sciclk 0x10 1111 parity error scpi parity error
78 at8xc5122/23 4202d?scr?06/05 alternate card a second card named ?alterna te card? can be controlled. the clock signal cclk1 can be adapted to the xtal frequency. thanks to the clock prescaler which can divide the frequency by 1, 2, 4 or 8. the bits altkps0 and altkps1 in scsr register ar e used to set this factor. figure 45. alternate card registers there are fifteen registers to control the scib macro-cell. they are described from table 58 to table 45. some of the register widths are greater than a byte. despite the 8 bits access provided by the biu, the address mapping of this kind of register respects the following rule : the low significant byte register is implemented at the higher address. this implementation makes access to these registers easier when using high level pro- gramming languages (c,c++). sim, sam card alternate card cvcc crst cio cclk ck_idle 1 0 cclk1 scsr reg. pr3 scclk1 1, 1/2, 1/4 or 1/8 p1.7 main card cpres smart card scsr reg. altkps0,1
79 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 44. smart card interface control register - scicr (s:b6h, scrs = 1) 76543210 reset carddet vcard1 vcard0 uart wten crep conv bit number bit mnemonic description 7 reset reset set this bit to reset and deactivate the smart card interface. clear this bit to activate the smart card interface. this bit acts as an active high software reset. 6 carddet card presence detector sense clear this bit to indicate the card presence detecto r is open when no card is inserted (cpres is high). set this bit to indicate the card presence detector is closed when no card is inserted (cpres is low). 5-4 vcard[1:0] card voltage selection: vcard[1] vcard[0 ] c vcc 00 0 v 0 1 1.8 v 1 0 3.0 v 1 1 5.0 v 3uart card uart selection clear this bit to use the cardio bit (p1.0) bit to drive the card i/o (p1.0) pin. set this bit to use the smart card uart to drive the card i/o pin (p1.0 pin). controls also the waiting time counter as described in section ?waiting time (wt) counter?, page 69 2wten waiting time counter enable clear this bit to stop the counter and enable the l oad of the waiting time counter hold registers. the hold registers are loaded with scwt0, scwt1, scwt2 and scwt3 values when scwt2 is written. set this bit to start the waiting time counter. t he counters stop when it reaches the timeout value. if the uart bit is set, the waiting time counter automatically reloads with the hold registers whenever a start bit is sent or received. 1crep character repetition clear this bit to disable parity er ror detection and indication on the card i/o pin in receive mode and to disable character repetition in transmit mode. set this bit to enable parity error indication on the card i/o pin in receive mode and to set automatic character repetition when a parity error is indicated in transmit mode. depending upon crepset bit is scsr register, the receiver can i ndicate parity error up to 4times (3 repetitions) or up to 5times (4 repetitions) after which it will raise the parity error bit scpe bit in the scisr register. if parity interrupt is enabled, the scpi bit in sciir register will be set too. alternately, the transmitter will detect icc character repetition request. after 3 or 4 unsuccessful repetitions (depending on crepsel bit in scsr register), the transmitter will raise the parity error bit scpe bit in the scisr register. if parity interrupt is enabled, the scpi bit in sciir register will be set too. note : character repetition mode is spec ified for t=0 protocol only and should not be used in t=1 protocol (block oriented protocol) 0conv iso convention clear this bit to use the direct convention: b0 bit (lsb) is sent first, the parity bit is added after b7 bit and a low level on the card i/o pin represents a?0?. set this bit to use the inverse convention: b7 bit (lsb) is s ent first, the parity bit is added after b0 bit and a low level on the card i/o pin represents a?1?.
80 at8xc5122/23 4202d?scr?06/05 reset value = 0x00 0000b table 45. smart card contacts regist er - sccon (s:ach, scrs=0) 76543210 clk - cardc8 cardc4 cardio cardclk cardrst cardvcc bit number bit mnemonic description 7clk card clock selection clear this bit to use the card clk bit (cardc lk bit below) to drive card clk (p1.4) pin. set this bit to use ck_xtal1 or ck _pll signals for ck_iso to drive t he card clk pin (cclk = p1.4 pin) note: internal synchronization avoids glitches on the clk pin when switching this bit. 6- reserved this bit can be changed by software but the read value is indeterminate. 5cardc8 card c8 clear this bit to drive a low level on the card c8 pin (cc8 = p1.1 pin). set this bit to set a high level on the card c8 pin (cc8 = p1.1 pin).. the cc8 pin can be used as a pseudo bi-d irectional i/o when this bit is set. warning : vcardok=1 (scisr.4 bit) condition mu st be true to change the state of cc8 pin 4cardc4 card c4 clear this bit to drive a low level on the card c4 pin (cc4 = p1.3 pin). set this bit to set a high level on the card c4 pin (cc4 = p1.3 pin). the cc4 pin can be used as a pseudo bi-d irectional i/o when this bit is set. warning : vcardok=1 (scisr.4 bit) condition mu st be true to change the state of cc4 pin 3 cardio card i/o if uart bit is cleared in scicr register, this bit enables the use of the card io pin (cio = p1.0) as a c51 pseudo bi-directional port : to read from cio (p1.0) port pin : set cardio (p1.0) bit then read cardio (p1.0) bit to have the cio port value to write in cio (p1.0) port pin : set cardio (p1.0) bit to write a 1 in cio (p1.0) port pin , clear cardio (p1.0) bit to write a 0 in cio (p1.0) port pin. warning : vcardok=1 (scisr.4 bit) condition mu st be true to change the state of cio pin 2 cardclk card clk when the clk bit is cleared in sccon register, the va lue of this bit is driven to the card clk pin. warning : vcardok=1 (scisr.4 bit) condition must be true to change the state of card clk pin 1 cardrst card rst clear this bit to drive a low level on the card rst pin. set this bit to set a high level on the card rst pin. warning : vcardok=1 (scisr.4 bit) condition must be true to change the state of card rst pin 0 cardvcc card vcc control clear this bit to desactivate the card interface and set its power-off. the other bits of sccon register have no effect while this bit is cleared. set this bit to power-on the card interface. the activation sequence shoul d be handled by software.
81 at8xc5122/23 4202d?scr?06/05 reset value = 1000 0000b table 46. smart card uart interf ace status register - scisr (s:adh, scrs=0) 76 5 4 3210 sctbe cardin icardovf vcardok scwto sctc scrc scpe bit number bit mnemonic description 7sctbe uart transmit buffer empty status this bit is set by hardware when the transmit buffer is copied to the transmit shift register of the smart card uart. it is cleared by hardware when scibuf register is written. 6cardin card presence status this bit is set by hardware if there is a card presence (debouncing filter has to be done by software). this bit is cleared by hardware if there is no card presence. 5icardovf card current overflow status this bit is set when the current on card is above the li mit specified by bit ovfadj in dcckps register (table 61 on page 94) it is cleared by hardware. 4 vcardok card voltage correct status this bit is set when the output voltage is within the vo ltage range specified by vcard[1:0] in scicr register. it is cleared otherwise. 3scwto waiting time counter timeout status this bit is set by hardware when t he waiting time counter has expired. it is cleared by the reload of the counter or by the reset of the scib. 2sctc uart transmitted character status this bit is set by hardware when the smart card uart ha s transmitted a character. if character repetition mode is selected, this bit will be set only after a successful transmi ssion. if the last allowed repet ition in not successful, this bit will not be set. it is cleared by software when this register is read. 1 scrc uart received character status this bit is set by hardware when the sm art card uart has received a character it is cleared by hardware when scibuf register is read. if c haracter repetition mode is selected, this bit will be set only after a successful reception. if the last allowed repetiti on is still unsuccessful, this bit will be set to let the user read the erroneous value if necessary. 0scpe character reception parity error status this bit is set when a parity error is detected on the received character. it is cleared by software when this register is read. if ch aracter repetition mode is select ed, this bit will be set only if the icc report an error on the last allowed repetition of a terminal transmission, or if a reception parity error is found on the last allowed icc character repetition.
82 at8xc5122/23 4202d?scr?06/05 reset value = 0x00 0000b note: 1) in case of multiple interrupts occuring at the same time (sampled by the same edge of the internal clock), the interrupts will be servic ed in the following order from the highest to the lowest priority : - uart transmit buffer empty - card current overflow - card voltage error - waiting time counter timeout - uart transmitted character - uart received character - character reception parity error 2) it is recommended that the application sa ves the sciir register after reading it in order to avoid the loss of pending interruptions as the sciir register is cleared when it is read by the mcu. table 47. smart card uart interrupt ident ification register (read only) sciir (s:aeh, scrs=0) 765 4 3210 sctbi - icarderr vcarderr scwti scti scri scpi bit number bit mnemonic description 7sctbi uart transmit buffer empty interrupt this bit is set by hardware when the transmit buffer is copied into the transmit shift register of the smart card uart. it generates an interrupt if esctbi bit is set in scier register otherwise this bit is irrelevant. it is cleared by hardware when this register is read. 6- reserved the value read from this bit is in determinate. do not change this bit. 5 icarderr card current overflow interrupt this bit is set when the current on card is above the li mit specified by bit ovfadj in dcckps register (table 61 on page 94). it generates an interrupt if icarder bit is set in scier register otherwise this bit is irrelevant. it is cleared by hardware when this register is read. 4 vcarderr card voltage error interrupt this bit is set when the output voltage goes out of t he voltage range specified by vcard field. it generates an interrupt if evcarder bit is set in scier register otherwise this bit is irrelevant. it is cleared by hardware when this register is read. 3scwti waiting time counter timeout interrupt this bit is set by hardware when the waiting time co unter has expired. it generates an interrupt if escwti bit is set in scier register ot herwise this bit is irrelevant. it is cleared by hardware when this register is read. 2scti uart transmitted character interrupt this bit is set by hardware when the smart card uart has completed the character transmission. it generates an interrupt if escti bit is set in scie r register otherwise this bit is irrelevant. it is cleared by hardware when this register is read. 1 scri uart received character interrupt this bit is set by hardware when the smart card uart has completed the character reception. it generates an interrupt if escri bit is set in scier r egister otherwise this bit is irrelevant. it is cleared by hardware when this register is read. 0scpi character reception parity error interrupt this bit is set at the same time as scti or scri if a parity error is detected on the received character. it generates an interrupt if escpi bit is set in scie r register otherwise this bit is irrelevant. it is cleared by hardware when this register is read.
83 at8xc5122/23 4202d?scr?06/05 reset value = 0x00 0000b table 48. smart card uart interrupt enabling register - scier (s:aeh, scrs=1) 765 4 3 2 1 0 esctbi - icarder evcarder escwti escti escri escpi bit number bit mnemonic description 7 esctbi uart transmit buffer empty interrupt enabled clear this bit to disable the smart card uart transmit buffer empty interrupt. set this bit to enable the smart card uart transmit buffer empty interrupt. 6- reserved the value read from this bit is i ndeterminate. do not change this bit. 5icarder card current overflow interrupt enabled clear this bit to disable the card current overflow interrupt. set this bit to enable the card current overflow interrupt. 4 evcarder card voltage error interrupt enabled clear this bit to disable the card voltage error interrupt. set this bit to enable the card voltage error interrupt. 3 escwti waitingtime counter timeout interrupt enabled clear this bit to disable the wait ing time counter timeout interrupt. set this bit to enable the waiting time counter timeout interrupt. 2 escti uart transmitted character interrupt enabled clear this bit to disable the smart ca rd uart transmitted character interrupt. set this bit to enable the smart card uart transmitted character interrupt. 1 escri uart received character interrupt enabled clear this bit to disable the smart card uart received character interrupt. set this bit to enable the smart card uart received character interrupt. 0 escpi character reception parity error interrupt enabled clear this bit to disable the smart card character reception parity error interrupt. set this bit to enable the smart card character reception parity error interrupt.
84 at8xc5122/23 4202d?scr?06/05 reset value = x000 1000b reset value = 0000 0000b table 49. smart card selection re gister - scsr (s:abh) 76543210 - bgten - crepsel altkps1 altkps0 scclk1 scrs bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not change this bit. 6bgten block guard time enable set this bit to select the minimum interval between t he leading edge of the start bits of the last character received from the icc and the first c haracter sent by the terminal. the tr ansfer of gt[8-0] value to the bgt counter is done on the rising edge of the bgten. clear this bit to suppress the minimum time between reception and transmission. 5- reserved the value read from this bit is i ndeterminate. do not change this bit. 4 crepsel character repetition selection clear this bit to select 5 times transmi ssion (1 original + 4 repetitions) befor e parity error indication (conform to emv) set this bit to select 4 times transmission (1 orig inal + 3 repetitions) before parity error indication 3-2 altkps1:0 alternate card clock prescaler factor 00 altkps = 0: prescaler factor equals 1 01 altkps = 1: prescaler factor equals 2 10 altkps = 2: prescaler factor equals 4 (reset value) 11 altkps = 3: prescaler factor equals 8 1scclk1 alternate card clock selection set to select the prescaled pr3 clock for cclk1 (p1.7) pin clear to select p1.7 port bit 0scrs smart card register selection the scrs bit selects which set of the scib registers is accessed. table 50. smart card transmit / rece ive buffer - scibuf (s:aa) 76543210 - ------- bit number bit mnemonic description -- smart card transmit / receive buffer - a new byte can be written in the buffer to be transmitted on the i/o pin when sctbe bit is set. the bits are sorted and copied on the i/o pin versus the active convention. - a new byte received from i/o pin is ready to be read when scri bit is set. the bits are sorted versus the active convention.
85 at8xc5122/23 4202d?scr?06/05 reset value = 0xxx x001b reset value = 0111 0100b table 51. smart card etu register 1 - scetu1 (s:adh, scrs=1) 76543210 comp----etu10etu9etu8 bit number bit mnemonic description 7comp compensation clear this bit when no time compensation is needed (i.e. w hen the etu to card clk period ratio is close to an integer with an error less than 1/4 of card clk period). set this bit otherwise and reduce the etu pe riod by 1 card clk cycle for even bits. 6-3 - reserved the value read from these bits is i ndeterminate. do not change these bits. 2-0 etu[10:8] etu msb used together with the etu lsb in scetu0 (table 52) warning : the etu counter is reloaded at each register?s write operation. do not change this register during character reception or transmission or while guard time or waiting time counters are running. table 52. smart card etu register 0 - scetu0 (s:ach, scrs=1) 76543210 etu7 etu6 etu5 etu4 etu3 etu2 etu1 etu0 bit number bit mnemonic description 7 - 0 etu[7:0] etu lsb the elementary time unit is (etu[10:0] - 0.5*comp)/f, where f is the card clk frequency. according to iso 7816, etu[10:0] can be set between 11 and 2048 (2047 ?) the default reset value of etu[10:0] is 372 (f=372, d=1).
86 at8xc5122/23 4202d?scr?06/05 reset value = 0000 1100b reset value = xxxx xxx0b reset value = 0000 0000b table 53. smart card transmit guard time register 0 - scgt0 (s:b4h, scrs=1) 76543210 gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 bit number bit mnemonic description 7 - 0 gt[7:0] transmit guard time lsb the minimum time between two consecutive start bits in tr ansmit mode is gt[8:0] * etu. this is equal to iso iec guard time +10 (see guard time counter description. according to iso iec 7816,the time between 2 consecut ive leading edge start bits can be set between 11 and 266 (11 to 254+12 etus). table 54. smart card transmit guard time register 1 - scgt1 (s:b5h, scrs=1) 76543210 -------gt8 bit number bit mnemonic description 7 - 1 - reserved the value read from these bits is i ndeterminate. do not change these bits. 0gt8 transmit guard time msb used together with the transmit guard time lsb in scgt0 register (table 53). table 55. smart card character/block waiting time register 3 scwt3 (s:c1h, scrs=0) 76543210 wt31 wt30 wt29 wt28 wt27 wt26 wt25 wt24 bit number bit mnemonic description 7 - 0 wt[31:24] waiting time byte3 used together with wt[23:0] in regist ers scwt2,scwt1, scwt0 (see table 56).
87 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b reset value = 0010 0101b reset value = 1000 0000b table 56. smart card character/block waiting time register 2 scwt2 (s:b6h, scrs=0) 76543210 wt23 wt22 wt21 wt20 wt19 wt18 wt17 wt16 bit number bit mnemonic description 7 - 0 wt[23:16] waiting time byte2 used together with wt[31:24] and wt[15:0] in registers scwt3,scwt1, scwt0 (see table 58). table 57. smart card character/block waiting time register 1 scwt1 (s:b5h, scrs=0) 76543210 wt15 wt14 wt13 wt12 wt11 wt10 wt9 wt8 bit number bit mnemonic description 7 - 0 wt[15:8] waiting time byte 1 used together with wt[31:16] and wt[7:0] in registers scwt3,scwt2, scwt0 (see table 55). table 58. smart card character/block waiting time register 0 scwt0 (s:b4h, scrs=0) 76543210 wt7 wt6 wt5 wt4 wt3 wt2 wt1 wt0 bit number bit mnemonic description 7 - 0 wt[7:0] waiting time byte 0 wt[31:0] is the reload value of the waiting time counter (wtc) . the wtc is a general-purpose timer. it is using the etu clock and is controlled by t he wten bit (see table 44 on page 79 and section ?waiting time (wt) counter?, page 69). when uart bit of registers is set, the wtc is automatica lly reloaded at each start bit of the uart. it is used to check the maximum time between to consecutive start bits.
88 at8xc5122/23 4202d?scr?06/05 reset value = 0x10 1111b (default value for a divider by two) dc/dc converter the smart card voltage (cvcc) is supplied by the integrated dc/dc converter which is controlled by several registers: ? the scicr register (table 44 on page 79) controls the cvcc level by means of bits vcard[1:0]. ? the sccon register (table 45 on page 80) enables to switch the dc/dc converter on or off by means of bit cardvcc. ? the dcckps register (table 61 on page 94) controls the dc/dc clo ck and current. the dc/dc converter cannot be switched on while the cpres pin remains inactive. if cpres pin becomes inactive while the dc/dc converter is operating an automatic shut down sequence of the dc/dc converte r is initiated by the electronics. it is mandatory to switch off the dc/dc conv erter before entering in power-down mode. configuration the dc/dc converter can work in two differ ent modes which are selected by bit mode in dcckps register: ? pump mode: an external inductance of 10 h must be connected between pins li and vcc. vcc can be higher or lower than cvcc. ? regulator mode : no external inductance is required but vcc must be always higher than cvcc+0.3v. the regulati on mode will work ev en if an external inductance of 10 h is connected between pins li and vcc the dc/dc clock prescaler which is cont rolled by bits dcckps[3:0], in dcckps regis- ter must be configured to set the dc/dc clock to a working frequency of 4 mhz which depends upon the value of the crystal. there is no need to change the default configura- tion set by the reset sequence if an 8 mhz crystal is used by the application. the dc/dc converter implements a current ov erflow controller which avoids permanent damage of the dc/dc converte r in case of short circui t between cvcc and cvss. the maximum limit is around 100 ma . it is possible to increase this limit in normal operating table 59. smart card clock reload register - sciclk (s:c1h, scrs=1) 7 6 543210 xtscs - sciclk5 sciclk4 sciclk3 sciclk2 sciclk1 sciclk0 bit number bit mnemonic description 7xtscs smart card clock selection bit if xtscs bit is set or ext48 bit is set (in pllc on register) , ck_pll is used to generate ck_iso. otherwise, ck_xtal1 is used to generate ck_iso. see the clock tree diagram figure 17. 6- reserved the value read from this bit is i ndeterminate. do not change these bits. 5 - 0 sciclk[5:0] scib clock reload register prescaler 2 reload value is used to defines the card clock frequency. if sciclk[5:0] is smaller than 48 : fck_iso = fck_pll or fck_xtal1/ (2 * (48 - sciclk[5:0])) if sciclk[5:0] is equal to 48 : fck_iso = fck_xtal1 sciclk[5:0] must be smaller than 49.
89 at8xc5122/23 4202d?scr?06/05 mode by 20% by means of bit ovfadj in dcckps register. when the current overflow controller is operating, the icardovf is set by the hardware in scisr register. the current drawn from power supply by t he dc/dc converter is controlled during the startup phase in order to avoid high transient current mainly in pump mode which could cause the power supply voltage to drop dramatically. this control is done by means of bits boost[1:0], which increases prog ressively the startup current level. initialization procedure the initialization procedure is different depen ding upon the required card vcc. one pro- cedure apply for card vcc =< 3 volts and one procedure for card vcc = 5 volts. the initialization pr ocedure involves : ? select the cvcc level by means of bits vcard[1:0] in scicr register, ? set bits boost[1:0] in d cckps register following the current level control wanted. ? switch the dc/dc on by means of bit cardvcc in sccon register, ? monitor bit vcardok in scisr regist er in order to know when the dc/dc converter is ready (cvcc voltage has reached the expected level) procedure for cvcc =< 3 volts the dc/dc regulation mode must be selected for card vcc = 1.8 volts and card vcc = 3 volts (mode = 1 in dcckps register) the detailed procedures is described in flow chart of figure 46. for card vcc = 1.8 volts and in the flow chart of figure 47. for card vcc = 3 volts
90 at8xc5122/23 4202d?scr?06/05 figure 46. card vcc = 1.8v initialization procedure mode regulation dcckps[7]=1 vcardok=1 set timeout to 3 ms timeout expired dc/dc initialization failure dc/dc initialization successful boost[1:0]=01 scicr.7=reset=0 scicr.7=reset=1 sccon cardvcc=1 vcard[1:0] = 01
91 at8xc5122/23 4202d?scr?06/05 figure 47. card vcc = 3v initialization procedure mode regulation dcckps[7]=1 vcardok=1 set timeout to 3 ms timeout expired dc/dc initialization failure dc/dc initialization successful boost[1:0]=01 scicr.7=reset=0 scicr.7=reset=1 sccon cardvcc=1 vcard[1:0] = 10
92 at8xc5122/23 4202d?scr?06/05 procedure for cvcc = 5volts the dc/dc pump mode must be selected (mode = 0 in dcckps register). the detailed procedure is described in flow chart of figure 48. vcc must be higher than 4.0 volts. figure 48. card vcc = 5v initialization procedure while vcc remains higher than 4.0v and startup current lower than 30 ma (depending on the load type), the dc/dc converter should be ready without having to increment boost[1:0] bits beyond [0:0] level. if vcc > 4.0v and startup curr ent > 30 ma, it will be necessary to increment the boost[1:0] bi ts until the dc/dc converter is ready. sccon cardvcc=1 vcardok=1 set timeout to 3 ms timeout expired increment boost [1:0] boost[1:0] = max = 3? dc/dc initialization failure dc/dc initialization successful decrement boost[1:0] to adjust the current overflow mode pump dcckps[7]=0 boost[1:0]=[0:0] scicr.7=reset=0 scicr.7=reset=1 vcard[1:0] = 11 boost[1:0] = [0:0]
93 at8xc5122/23 4202d?scr?06/05 incrementation of boost[1:0] bits increases at the same time the current overflow level in the same proportion as the startup current. so once the dc/dc converter is ready it is advised to decrement the boost[ 1:0] bits to restore the overflow current to its normal or desired value. monitoring procedure once the dc/dc has been successfuly initializ ed, it is necessary to monitor the dc/dc converter by means of bits vcardok and icardovf in the scisr register. table 60. dc/dc converter status vcardok icardovf dc/dc status 00 - not started or switched off by application. the current overflow sensor is disabled during the dc/dc converter startup. then if a current overflow condition is applied during the dc/dc converter start up, the dc/dc converter is unable to start and both bits vcardok and icardovf remains at 0. dc/dc converter correctly started then the output voltage is out of iso/iec 7816-3 specifications. in this case the firmware mu st take appropriate actions like deactivating the dc/dc converter in compliance with iso/iec 7816. 0 1 started and automatically switched off by a current overflow condition 1 0 operating properly according to iso/iec 7816-3 and emv recommendations 1 1 not applicable
94 at8xc5122/23 4202d?scr?06/05 dc/dc converter register reset value = 0000 0000b table 61. dc/dc converter control re gister - dcckps (s:bfh) 76543210 mode ovfadj boost1 boost0 dcc kps3 dcckps2 dcckps1 dcckps0 bit number bit mnemonic description 7mode regulation mode 0 : pump mode (external inductance required) 1 : regulator mode (no external induc tance required if vcc > cvcc+0.3v) 6 ovfadj current overflow adjustment on smart card terminal 0 : normal: 100 ma average 1 : normal + 20% 5 - 4 boost[1:0] vcardok=0 vcardok=1 maximum startup current drawn from power supply 00 : normal: 30 ma average 01 : normal + 30% 10 : normal + 50% 11 : normal + 80% current overflow level on smart card terminal 00 : normal = ovfadj 01 : normal + 30% 10 : normal + 50% 11 : normal + 80% 3 - 0 dcckps[3:0] dc/dc clock prescaler value 0000 : division factor: 2 (reset value) 0001 : division factor: 3 0010 : division factor: 4 0011 : division factor: 5 0100 : division factor: 6 0101 : division factor: 8 0110 : division factor: 10 0111 : division factor: 12 1000 : division factor: 24 other values are reserved
95 at8xc5122/23 4202d?scr?06/05 usb controller the at8xc5122d implements a usb device controller supporting full speed data transfer. in addition to the default control end point 0, it provides 6 other endpoints, which can be configured in control, bu lk, interrupt or isochronous modes: ? endpoint 0: 32-byte fifo, default control endpoint ? endpoint 1,2,3: 8-byte fifo ? endpoint 4,5: 64-byte fifo ? endpoint 6: 2 x 64-byte ping-pong fifo this allows the firmware to be developed c onforming to most us b device classes, for example: ? usb mass storage class control/bulk/interrupt (cbi) transport, revision 1.0 - december 14, 1998. ? usb mass storage class bulk-only transport, revision 1.0 - september 31, 1999. ? usb human interface device class, version 1.1 - april 7, 1999. ? usb device firmware upgrade class, revision 1.0 - may 13, 1999. usb mass storage classes usb mass storage class cbi transport within the cbi framework, the control endpoi nt is used to transport command blocks as well as to transport standard usb requests. on e bulk-out endpoint is used to transport data from the host to the device. one bulk-in endpoint is used to transport data from the device to the host. and one interrupt endpoint may also be used to signal command completion (protocol 0); it is optiona l and may not be used (protocol 1). the following configuration adheres to these requirements: ? endpoint 0: 8 bytes, control in-out ? endpoint 4: 64 bytes, bulk-out ? endpoint 5: 64 bytes, bulk-in ? endpoint 1: 8 bytes, interrupt in usb mass storage class bulk- only transport within the bulk-only framework, the control endpoint is only used to transport class- specific and standard usb requests for device set-up and configuration. one bulk-out endpoint is used to transport commands and data from the host to the device. one bulk- in endpoint is used to transport status and da ta from the device to the host. no interrupt endpoint is needed. the following configuration adheres to these requirements: ? endpoint 0: 8 bytes, control in-out ? endpoint 4: 64 bytes, bulk-out ? endpoint 5: 64 bytes, bulk-in usb device firmware upgrade (dfu) the usb device firmware update (dfu) protocol can be used to upgrade the on-chip program memory of the at8xc5122d. this allows the implementation of product enhancements and patches to devices that are already in the field. two different config- urations and description sets are used to support dfu functions. the run-time configuration co-exists with the usual func tions of the device, which may be usb mass storage for the at8xc5122d. it is used to initiate dfu from the normal operating mode. the dfu configuration is used to perform t he firmware update after device re-configura- tion and usb reset. it excludes any other function. only the default control pipe (endpoint 0) is used to support df u services in both configurations.
96 at8xc5122/23 4202d?scr?06/05 the only possible value for the wmaxpacket size in the dfu configuration is 32 bytes, which is the size of the fifo implemented for endpoint 0. description the usb device controller provides the hardware that the at8xc5122d and the at83c5123 need to interface a usb link to a data flow stored in a double port memory (dpram). the usb controller requires a 48 mhz reference clock, which is the output of the at8xc5122d/23 pll (see section "phase lock loop (pll)", page 42) divided by a clock prescaler. this clock is used to generate a 12 mhz full speed bit clock from the received usb differential data and to transmi t data according to full speed usb device tolerance. clock recovery is done by a dig ital phase locked loop (dpll) block, which is compliant with th e jitter specificati on of the usb bus. the interface engine (sie) block perfo rms nrzi encoding and decoding, bit stuffing, crc generation and checking, and the serial -parallel data conver sion. the universal function interface (ufi) performs the interf ace between the data flow and the dual port ram figure 49. usb device controller block diagram serial interface engine (sie) the sie performs the following functions: ? nrzi data encoding and decoding. ? bit stuffing and unstuffing. ? crc generation and checking. ? handshakes. ? token type identifying. ? address checking. ? clock generation (via dpll). sie dpll usb d+/d- buffer ufi 12mhz 48 mhz +/- 0.25% d+ up to 48 mhz uc_sysclk c51 microcontroller interface d-
97 at8xc5122/23 4202d?scr?06/05 figure 50. sie block diagram function interface unit (ufi) the function interface unit provides the interface between the at8xc5122d (or at83c5123) and the sie. it manages transacti ons at the packet leve l with minimal inter- vention from the device firmware, which reads and writes the endpoint fifos. figure 51. ufi block diagram end of packet detection start of packet detection d+ d- clock recovery sync detection pid decoder address decoder serial to parallel conversion crc5 & crc16 generation/check usb pattern generator parallel to serial converter bit stuffing nrzi converter crc16 generator nrzi ? nrz bit unstuffing packet bit counter clk48 (48 mhz) sysclk (12 mhz) datain [7:0] dataout 8 8 transfer control fsm dpr control usb side csreg 0 to 7 registers bank dpr control mp side ufi user dpram up to 48 mhz uc_sysclk c51 microcontroller interface asynchronous information transfer endpoint 0 endpoint 1 endpoint 2 endpoint 3 sie dpll endpoint 4 endpoint 5 endpoint 6
98 at8xc5122/23 4202d?scr?06/05 figure 52. minimum intervention from the usb device firmware out transactions: host ufi c51 out data0 (n bytes) ack endpoint fifo read (n bytes) out data1 nack out data1 ack in transactions: host ufi c51 in ack endpoint fifo write in data1 nack interrupt c51 in data1 interrupt c51 endpoint fifo write
99 at8xc5122/23 4202d?scr?06/05 configuration general configuration ? usb controller enable before any usb transaction, the 48 mhz required by the usb controller must be cor- rectly generated (section "clock controller", page 41). the usb controller should be then enabled by setting the usbe bit in the usbcon register. ? set address after a reset or a usb reset, the software has to set the fen (function enable) bit in the usbaddr register. this action will a llow the usb controller to answer to the requests sent at the address 0. when a set_address request has been received, the usb controller must only answer to the address defined by the reques t. the new address should be stored in the usbaddr register. the fen bit and the fadde n bit in the usbcon register should be set to allow the usb controller to answer only to requests sent at the new address. ? set configuration the confg bit in the usbcon register should be set after a set_configuration request with a non-zero value. otherwise, this bit should be cleared. endpoint configuration ? selection of an endpoint the endpoint register access is performed us ing the uepnum register. the following registers correspond to the endpoint whose number is stored in the uepnum register. to select an endpoint, the firmware has to write the endpoint number in the uepnum register. ? uepstax, ? uepconx, ? uepdatx, ? ubyctx, figure 53. endpoint selection uepnum endpoint 0 endpoint 6 uepsta0 uepcon0 uepdat0 uepsta6 uepcon6 uepdat6 0 1 2 3 4 5 6 sfr registers uepstax uepconx uepdatx x ubyct0 ubyct6 ubyctx
100 at8xc5122/23 4202d?scr?06/05 ? endpoint enable before using an endpoint, this one should be enabled by setting the epen bit in the uepconx register. an endpoint which is not enabled won?t answer to any usb request. the default control endpoint (endpoint 0) should always be enabled in order to answer to usb standard requests. ? endpoint type configuration all standard endpoints can be configured in control, bulk, interrupt or isochronous mode. the ping-pong endpoints can be configured in bulk, interrupt or isochronous mode. the configurat ion of an endpoint is performed by setti ng the field eptype with the following values: ? control: eptype = 00b ? isochronous: eptype = 01b ? bulk: eptype = 10b ? interrupt: eptype = 11b the endpoint 0 is the defaul t control endpoint and should always be configured in con- trol type. ? endpoint direction configuration for bulk, interrupt and isochronous endpoints , the direction is defined with the epdir bit of the uepconx register with the following values: ? in:epdir = 1b ? out:epdir = 0b for control endpoints, the epdir bit has no effect. ? summary of endpoint configuration: make sure to select the correct endpoint number in the uepnum register before accessing to endpoint specific registers. table 62. summary of endpoint configuration endpoint configuratio n epen epdir eptype uepconx disabled 0b xb xxb 0xxx xxxb control 1b xb 00b 80h bulk-in 1b 1b 10b 86h bulk-out 1b 0b 10b 82h interrupt-in 1b 1b 11b 87h interrupt-out 1b 0b 11b 83h isochronous-in 1b 1b 01b 85h isochronous-out 1b 0b 01b 81h
101 at8xc5122/23 4202d?scr?06/05 ? endpoint fifo reset before using an endpoint, its fifo should be reset. this action re sets the fifo pointer to its original value, rese ts the byte counter of the endpoint (ubyctx register), and resets the data toggle bi t (dtgl bit in uepconx). the reset of an endpoint fifo is performed by setting to 1 and resetting to 0 the corre- sponding bit in the ueprst register. for example, in order to reset the endpoint number 2 fifo, write 0000 0100b then 0000 0000b in the ueprst register.
102 at8xc5122/23 4202d?scr?06/05 read/write data fifo read data fifo the read access for each out endpoint is performed using the uepdatx register. after a new valid packet has been received on an endpoint, the data are stored into the fifo and the byte counter of the endpoint is updated (ubyctx register). the firmware has to store the endpoint byte counter before any access to the endpoint fifo. the byte counter is not updated when reading the fifo. to read data from an endpoint, select the correct endpoint number in uepnum and read the uepdatx register. this action automatically decreases the corresponding address vector, and the next data is th en available in the uepdatx register. write data fifo the write access for each in endpoint is performed using the uepdatx register. to write a byte into an in endpoint fifo, select the correct endpoint number in uep- num and write into the uepdatx register. the corresponding address vector is automatically increased, and another write can be carried out. warning 1: the byte counter is not updated. warning 2: do not write more bytes than supported by the corresponding endpoint. figure 54. endpoint fifo configuration endpoint 0 - bank 0 endpoint 1 - bank 0 endpoint 2 - bank 0 endpoint 3 - bank 0 endpoint 4 - bank 0 endpoint 5 - bank 0 endpoint 6 - bank 0 endpoint 6 - bank 1 8 bytes 32 bytes 8 bytes 8 bytes 64 bytes 2 x 64 bytes base addresses 00h 20h 28h 30h 38h 78h b8h f8h 138h 64 bytes
103 at8xc5122/23 4202d?scr?06/05 bulk / interrupt transactions bulk and interrupt transactions are managed in the same way. bulk/interrupt out transactions in standard mode figure 55. bulk/interrupt out transactions in standard mode an endpoint should be first enabled and configured before being able to receive bulk or interrupt packets. when a valid out packet is received on an endpoint, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the cor- responding endpoint, store the number of da ta bytes by reading the ubyctx register. if the received packet is a zlp (zero length pa cket), the ubyctx register value is equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, the firmware should clear the rxoutb0 bit to allow the usb controller to accept the next out packet on this end- point. until the rxoutb0 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests. if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb c ontroller will consider that the packet is valid if the crc is correct and the endpoint byte counter contains the number of bytes sent by the host. out data0 (n bytes) ack host ufi c51 endpoint fifo read byte 1 out data1 nak rxoutb0 endpoint fifo read byte 2 endpoint fifo read byte n clear rxoutb0 out data1 nak out data1 ack rxoutb0 endpoint fifo read byte 1
104 at8xc5122/23 4202d?scr?06/05 bulk/interrupt out transactions in ping-pong mode (endpoints 6) figure 56. bulk / interrupt out transactions in ping-pong mode an endpoint should be first enabled and configured before being able to receive bulk or interrupt packets. when a valid out packet is received on t he endpoint bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corresponding endpoint, store the number of data bytes by reading the ubyctx regis- ter. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, the firmware should clear the rxoub0 bit to allow the usb controller to accept the next out packet on the endpoint bank 0. this action switches the endpoint bank 0 and 1. until the rxoutb0 bit has been cleared by the firmwar e, the usb controller will answe r a nak handshake for each out requests on the bank 0 endpoint fifo. when a new valid out packet is received on the endpoint bank 1, the rxoutb1 bit is set by the usb controller. this triggers an in terrupt if enabled. the firmware empties the bank 1 endpoint fifo before clearing the rxoutb1 bit. until the rxoutb1 bit has been cleared by the firmwar e, the usb controller will answe r a nak handshake for each out requests on the bank 1 endpoint fifo. the rxoutb0 and rxoutb1 bits are alternat ively set by the usb controller at each new valid packet receipt. the firmware has to clear one of these two bits after having read all the data fifo to allow a new valid packet to be stored in the corresponding bank. a nak handshake is sent by the usb contro ller only if the banks 0 and 1 has not been released by the firmware. out data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - read byte 1 rxoutb0 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte n clear rxoutb0 out data1 (m bytes) ack rxoutb1 endpoint fifo bank 1 - read byte 1 endpoint fifo bank 1 - read byte 2 endpoint fifo bank 1 - read byte m clear rxoutb1 out data0 (p bytes) ack rxoutb0 endpoint fifo bank 0 - read byte 1 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte p clear rxoutb0
105 at8xc5122/23 4202d?scr?06/05 if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb c ontroller will consider that the packet is valid if the crc is correct. bulk/interrupt in transactions in standard mode figure 57. bulk/interrupt in transactions in standard mode an endpoint should be first enabled and configured before being able to send bulk or interrupt packets. the firmware should fill the fifo with the dat a to be sent and set the txrdy bit in the uepstax register to allow the usb controlle r to send the data stored in fifo at the next in request concerning this endpoint. to send a zero length packet, the firmware should set the txrdy bit without writing any data into the endpoint fifo. until the txrdy bit has been set by the firmware, the usb controller will answer a nak handshake for each in requests. to cancel the sending of this packet, the firmware has to reset the txrdy bit. the packet stored in the endpoint fifo is then cleared and a new packet can be written and sent. when the in packet has been sent and acknowledged by the host, the txcmpl bit in the uepstax register is set by the usb c ontroller. this triggers a usb interrupt if enabled. the firmw are should clear the txcmpl bit be fore filling the endpoint fifo with new data. the firmware should never write more by tes than supported by the endpoint fifo. all usb retry mechanisms are automatically managed by the usb controller. in data0 (n bytes) ack host ufi c51 endpoint fifo write byte 1 in nak txcmpl endpoint fifo write byte 2 endpoint fifo write byte n set txrdy clear txcmpl endpoint fifo write byte 1
106 at8xc5122/23 4202d?scr?06/05 bulk/interrupt in transactions in ping-pong mode figure 58. bulk / interrupt in transa ctions in ping-pong mode an endpoint will be first enabled and configured bef ore being able to send bulk or inter- rupt packets. the firmware will fill the fifo bank 0 with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning the endpoint. t he fifo banks are automatically switched, and the firmware can immediately write into the endpoint fifo bank 1. when the in packet concerning the bank 0 has been sent and acknowledged by the host, the txcmpl bit is set by the usb co ntroller. this triggers a usb interrupt if enabled. the firmware will clea r the txcmpl bit before filli ng the endpoint fifo bank 0 with new data. the fifo banks ar e then automatically switched. when the in packet concerning the bank 1 has been sent and acknowledged by the host, the txcmpl bit is set by the usb co ntroller. this triggers a usb interrupt if enabled. the firmware will clea r the txcmpl bit before filli ng the endpoint fifo bank 1 with new data. the bank switch is performed by the usb cont roller each time the txrdy bit is set by the firmware. until the txrdy bit has been set by the firmware for an endpoint bank, the usb controller will answer a nak hands hake for each in requests concerning this bank. note that in the example above, the firmware clears the transmit complete bit (txc- mpl) before setting the transmit ready bit (t xrdy). this is done in order to avoid the firmware to clear at the same time the txcmpl bit for bank 0 and the bank 1. the firmware will never writ e more bytes than suppor ted by the endpoint fifo. in data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - write byte 1 in nack txcmpl endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte n set txrdy endpoint fifo bank 1 - write byte 1 endpoint fifo bank 1 - write byte 2 endpoint fifo bank 1 - write byte m set txrdy in data1 (m bytes) ack endpoint fifo bank 0 - write byte 1 endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte p set txrdy clear txcmpl in data0 (p bytes) ack txcmpl clear txcmpl endpoint fifo bank 1 - write byte 1
107 at8xc5122/23 4202d?scr?06/05 control transactions setup stage the dir bit in the uepstax re gister should be at 0. receiving setup packets is the same as re ceiving bulk out packets, except that the rxsetup bit in the uepstax register is set by the us b controller instead of the rxoutb0 bit to indicate that an out packet with a setup pid has been received on the control endpoint. when the rxse tup bit has been set, all th e other bits of the uep- stax register are cleared and an interrupt is triggered if enabled. the firmware has to read the setup request stored in the control endpoint fifo before clearing the rxsetup bit to free the en dpoint fifo for the next transaction. data stage: control endpoint direction the data stage management is similar to bulk management. a control endpoint is managed by the usb controller as a full-duplex endpoint: in and out. all other endpoint types are managed as half-duplex endpoint: in or out. the firmware has to specify the control endpoint di rection for the data stage using the dir bit in the uepstax register. ? if the data stage consists of ins, the firmware has to set the dir bit in the uepstax register before writing into the fifo and sending the data by setting to 1 the txrdy bit in the uepstax register. the in transaction is complete when th e txcmpl has been se t by the hardware. the firmware should clear the txcmpl bit before any other transaction. ? if the data stage consists of outs, the firmware has to leave the dir bit at 0. the rxoutb0 bit is set by hardware when a new valid packet has been received on the endpoint. the firmware must read the data stored into the fifo and then clear the rxoutb 0 bit to reset the fifo and to allow the next transaction. the bit dir is used to send the corr ect data toggle in the data stage. to send a stall handshake, see ?stall handshake? on page 110. status stage the dir bit in the uepstax register should be reset at 0 for in and out status stage. the status stage management is similar to bulk management. ? for a control write transaction or a no-data control transaction, the status stage consists of a in zero length packet (s ee ?bulk/interrupt in transactions in standard mode? on page 105). to send a stall handshake, see ?stall handshake? on page 110. ? for a control read transaction, the status stage consists of a out zero length packet (see ?bulk/interrupt out transactions in standard mode? on page 103).
108 at8xc5122/23 4202d?scr?06/05 isochronous transactions isochronous out transactions in standard mode an endpoint should be first enabled and conf igured before being able to receive isochro- nous packets. when an out packet is received on an en dpoint, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corre- sponding endpoint, store the number of data bytes by reading the ubyctx register. if the received packet is a zlp (zero length pa cket), the ubyctx register value is equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by the usb controller if the packet stored in fifo has a corrupted crc. this bit is update d after each new packet receipt. when all the endpoint fifo bytes have been read, the firmware should clear the rxoutb0 bit to allow the usb controller to store the next out packet data into the endpoint fifo. until the rxou tb0 bit has been cleared by the firmware, the data sent by the host at each ou t transaction will be lost. if the rxoutb0 bit is cleared while the host is sending data, the usb controller will store only the remaining bytes into the fifo. if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb c ontroller will consider that the packet is valid if the crc is correct. isochronous out transactions in ping-pong mode an endpoint should be first enabled and conf igured before being able to receive isochro- nous packets. when a out packet is received on the endpoi nt bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the cor- responding endpoint, store the number of da ta bytes by reading the ubyctx register. if the received packet is a zlp (zero length pa cket), the ubyctx register value is equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by the usb controller if the packet stored in fifo has a corrupted crc. this bit is update d after each new packet receipt. when all the endpoint fifo bytes have been read, the firmware should clear the rxoub0 bit to allow the usb controller to store the next out packet data into the end- point fifo bank 0. this action switches t he endpoint bank 0 and 1. until the rxoutb0 bit has been cleared by the firmware, the data sent by the host on the bank 0 endpoint fifo will be lost. if the rxoutb0 bit is cleared while the host is sending data on the endpoint bank 0, the usb controller will store only the remaining bytes into the fifo. when a new out packet is received on the endpoint bank 1, the rxoutb1 bit is set by the usb controller. this triggers an inte rrupt if enabled. the firmware empties the bank 1 endpoint fifo before clearing the rxoutb1 bit. until the rxoutb1 bit has been cleared by the firmware, the data sent by the host on the bank 1 endpoint fifo will be lost. the rxoutb0 and rxoutb1 bits are alternat ively set by the usb controller at each new packet receipt. the firmware has to clear one of these two bits after having read all the data fifo to allow a new packet to be stored in the corresponding bank.
109 at8xc5122/23 4202d?scr?06/05 if the host sends more bytes than supported by the endpoint fifo, the overflow data won?t be stored, but the usb c ontroller will consider that the packet is valid if the crc is correct. isochronous in transactions in standard mode an endpoint should be first enabled and configured before being able to send isochro- nous packets. the firmware should fill the fifo with the dat a to be sent and set the txrdy bit in the uepstax register to allow the usb controlle r to send the data stored in fifo at the next in request concerning this endpoint. if the txrdy bit is not set wh en the in request occurs, no thing will be sent by the usb controller. when the in packet has been sent, the txcmpl bit in the uepstax register is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo with new data. the firmware should never write more bytes than supported by the endpoint fifo. isochronous in transactions in ping-pong mode an endpoint should be first enabled and configured before being able to send isochro- nous packets. the firmware should fill the fifo bank 0 with the data to be sent and set the txrdy bit in the uepstax register to allo w the usb controller to send the data stored in fifo at the next in request concerning the endpo int. the fifo banks are automatically switched, and the firmware can immediatel y write into the endpoint fifo bank 1. if the txrdy bit is not set wh en the in request occurs, no thing will be sent by the usb controller. when the in packet concerning the bank 0 has been sent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo bank 0 with new data. the fifo banks are then automatically switched. when the in packet concerning the bank 1 has been sent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before f illing the endpoint fifo bank 1 with new data. the bank switch is performed by the usb cont roller each time the txrdy bit is set by the firmware. until the txrdy bit has been set by the firmware for an endpoint bank, the usb controller won?t send anything at each in requests concerning this bank. the firmware should never write more by tes than supported by the endpoint fifo.
110 at8xc5122/23 4202d?scr?06/05 miscellaneous usb reset the eorint bit in the usbint register is set by hardware when a end of reset has been detected on the usb bus. this triggers a usb interrupt if enabled. the usb con- troller is still enabled, but all the usb registers are rese t by hardware. the firmware should clear the eorint bit to a llow the next usb reset detection. stall handshake this function is only available for control, bulk, and interrupt endpoints. the firmware has to set the stallrq bit in the uepstax register to send a stall handshake at the next request of the host on the endpoint selected with the uepnum register. the rxsetup, txrdy, txcmpl, rxoutb0 and rxou tb1 bits must be first reset to 0. the bit stlcrc is set at 1 by the usb controller when a stall has been sent. this triggers an interrupt if enabled. the firmware should clear the stallrq and stlcrc bits after each stall sent. the stallrq bit is cleared automatically by hardware when a valid setup pid is received on a control type endpoint. start of frame detection the sofint bit in the usbint register is set when the us b controller detects a start of frame pid. this triggers an interrupt if enabled. the firmware should clear the sofint bit to allow the next start of frame detection. frame number when receiving a start of frame, the frame number is automatically stored in the ufnuml and ufnumh registers. the crcok and crcerr bits indicate if the crc of the last start of frame is valid (crcok se t at 1) or corrupt (crcerr set at 1). the ufnuml and ufnumh registers are automatically updated when receiving a new start of frame. data toggle bit the data toggle bit is set by hardware wh en a data 0 packet is received and accepted by the usb controller and cleared by hardw are when a data 1 packet is received and accepted by the usb controller. this bit is reset when the firmware resets the endpoint fifo using the ueprst register. for control endpoints, each setup transaction starts with a data 0 and data toggling is then used as for bulk endpoints until the end of the data stage (for a control write transfer). the status stage completes the data transfer with a data 1 (for a control read transfer). for isochronous endpoints, the device fi rmware should ignore the data-toggle. nak handshakes when a nak handshake is sent by the usb co ntroller to a in or out request from the host, the nakin or nakout bit is set by hardware. this information can be used to determine the direction of the communication during a control transfer. these bits are cleared by software.
111 at8xc5122/23 4202d?scr?06/05 suspend/resume management suspend the suspend state can be dete cted by the usb controller if all the clocks are enabled and if the usb controller is enabled. the bit spint is set by hardware when an idle state is detected for more than 3 ms. this triggers a usb interrupt if enabled. in order to reduce current consumption, th e firmware can put the usb pad in idle mode, stop the clocks and put the c51 in idle or power-down mode. the resume detection is still active. the usb pad is put in idle mode when the firmware clear the spint bit. in order to avoid a new suspend detection 3ms later, t he firmware has to disable the usb clock input using the suspclk bit in the usbcon register. the usb pad automatically exits of idle mode when a wake-up event is detected. the stop of the 48 mhz clock from the pll should be done in the following order: 1. disable of the 48 mhz clock input of th e usb controller by setting to 1 the sus- pclk bit in the usbcon register. 2. disable the pll by clearing the pllen bit in the pllcon register. resume when the usb controller is in suspend state, the resume detection is active even if all the clocks are disabled and if the c51 is in idle or power-down mode. the wupcpu bit is set by hardware when a non-idle state occurs on the usb bus. this triggers an inter- rupt if enabled. this interrupt wakes up the cpu from its idle or power-down state and the interrupt function is th en executed. the firmware will first enable th e 48 mhz gener- ation and then reset to 0 the suspclk bit in the usbcon register if needed. the firmware has to clear the spint bit in the usbint register before any other usb operation in order to wake up the usb controller from its suspend mode. the usb controller is then re-activated.
112 at8xc5122/23 4202d?scr?06/05 figure 59. example of a suspend/resume management upstream resume a usb device can be allowed by the host to send an upstream resume for remote wake-up purpose. when the usb controller receives the set_feature request: device_remote_wakeup, the firmware sh ould set to 1 the rmwupe bit in the usbcon register to enable this functi on. rmwupe value should be 0 in the other cases. if the device is in suspend mode, the usb controller can s end an upstr eam resume by clearing first the spint bit in the usbint re gister and by setting then to 1 the sdrm- wup bit in the usbcon register. the usb c ontroller sets to 1 the uprsm bit in the usbcon register. all clocks must be enabled first. the remote wake is sent only if the usb bus was in suspend state for at least 5 ms. when the upstream resume is com- pleted, the uprsm bit is reset to 0 by hardware. the firmware should then clear the sdrmwup bit. usb controller init detection of a suspend state spint set suspclk disable pll microcontroller in power-down detection of a resume state wupcpu enable pll clear suspclk clear wupcpu bit clear spint note : wupcpu bit must be cleared before enabling the pll put the usb pads in power down mode
113 at8xc5122/23 4202d?scr?06/05 figure 60. example of remote wakeup management usb controller init detection of a suspend state spint set rmwupe suspend management enable clocks upstream resume sent uprsm clear spint set sdmwup clear sdrmwup set_feature: device_remote_wakeup need usb resume uprsm = 1
114 at8xc5122/23 4202d?scr?06/05 detach simulation in order to be re-enumerate d by the host, the at8xc5122/2 3 has the possibility to sim- ulate a detach-attach of the usb bus. the v ref output voltage is between 3.0v and 3.6v. this output can be connected to the d+ pull-up as shown in figure 61. this output can be put in high-impedance when the detach bit is set to 1 in the usbcon r egister. maintaining this output in high imped- ance for more than 3 s will simulate the disconnection of the device. when resetting the detach bit, an attach is then simula ted. the usb controller should be enabled to use this feature. figure 61. example of v ref connection figure 62. disconnect timing d- d+ d- d+ gnd vcc v ref r1 usb-b connector 1 2 3 4 r2 r3 d+ d- v ss v il v ihz(min) device disconnected disconnect detected >= 2,5 s
115 at8xc5122/23 4202d?scr?06/05 usb interrupt system interrupt syst em priorities figure 63. usb interrupt control system interrupt control system as shown in figure 64, many events can produce a usb interrupt: ? txcmpl: transmitted in data (table 70 on page 121). this bit is set by hardware when the host accept a in packet. ? rxoutb0: received out data bank 0 (table 70 on page 121). this bit is set by hardware when an out packet is accepted by the endpoint and stored in bank 0. ? rxoutb1: received out data bank 1 (only for ping-pong endpoints) (table 70 on page 121). this bit is set by hardware w hen an out packet is accepted by the endpoint and stored in bank 1. ? rxsetup: received setup (table 70 on page 121). this bit is set by hardware when an setup packet is accepted by the endpoint. ? nakin and nakout: these bits are set by hardware when a nak handshake has been received on the corresponding endpoint. these bits are cleared by software. ? stlcrc: stalled (only for control, bulk and interrupt endpoints) (table on page 122). this bit is set by hardware when a stall handshake has been sent as requested by stallrq, and is reset by hardware when a setup packet is received. ? sofint: start of frame interrupt (table 65 on page 118). this bit is set by hardware when a usb start of frame packet has been received. ? wupcpu: wake-up cpu interrupt (table 65 on page 118). this bit is set by hardware when a usb resume is detected on the usb bus, after a suspend state. ? spint: suspend interrupt (table 65 on page 118). this bit is set by hardware when a usb suspend is detected on the usb bus. eusb ien1.6 ea ien0.7 usb controller iph/l interrupt enable lowest priority interrupts priority enable 00 01 10 11 d+ d- table 63. priority levels iphusb iplusb usb priority level 0 0 0 lowest 01 1 10 2 1 1 3 highest
116 at8xc5122/23 4202d?scr?06/05 figure 64. usb interrupt control block diagram txcmp uepstax.0 rxoutb0 uepstax.1 rxsetup uepstax.2 stlcrc uepstax.3 epxie uepien.x epxint uepint.x sofint usbint.3 esofint usbien.3 spint usbint.0 espint usbien.0 eusb ie1.6 endpoint x (x = 0..6) eorint usbint.4 wupcpu usbint.5 ewupcpu usbien.5 rxoutb1 uepstax.6 eeorint usbien.4 nakout uepconx.5 nakin uepconx.4 nakien uepconx.6
117 at8xc5122/23 4202d?scr?06/05 registers reset value = 0000 0000b table 64. usb global control register - usbcon (s:bch) 76 5 43210 usbe suspclk sdrmwup detach uprsm rmwupe confg fadden bit number bit mnemonic description 7usbe usb enable set this bit to enable the usb controller. clear this bit to disable and reset t he usb controller, to disable the usb transceiver and to disable the usb controller clock inputs. 6 suspclk suspend usb clock set this bit to disable the 48mhz clock input (resume detectio n is still active). clear this bit to enable the 48mhz clock input. 5sdrmwup send remote wake-up set this bit to force an external interrupt on the usb controller for remote wake up purpose. an upstream resume is send only if the bit rmwupe is set, all usb clocks are enabled and the usb bus was in suspend state for at least 5 ms. see uprsm below. this bit is cleared by software. 4detach detach command set this bit to simulate a detach on the usb line. the v ref pin is then in a floating state. clear this bit to maintain v ref at 3.3v. 3uprsm upstream resume (read only) this bit is set by hardware when sdrmwup has been set and if rmwupe is enabled. this bit is cleared by hardware afte r the upstream resume has been sent. 2rmwupe remote wake-up enable set this bit to enabled request an upst ream resume signaling to the host. clear this bit otherwise. note: do not set this bit if the host has not set the device_remote_wakeup feature for the device. 1confg configured this bit should be set by the device firmware after a set_configuration request with a non-zero value has been correctly processed. it should be cleared by the device firmware when a set_configuration request with a zero value is received. it is cleared by hardware on hardware reset or when an usb reset is detected on the bus (se0 state for at least 32 full speed bit times: typically 2.7 s). 0 fadden function address enable this bit should be set by t he device firmware after a successful status phase of a set_address transaction. it should not be cleared afterwards by the device firmware. it is cleared by hardware on hardware reset or when an usb reset is received (see above). when this bit is cleared, the def ault function address is used (0).
118 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 65. usb global interrupt regi ster - usbint (s:bdh) 76543210 - - wupcpu eorint sofint - - spint bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not change these bits. 5 wupcpu wake-up cpu interrupt this bit is set by hardware when the u sb controller is in suspend state and is re-activated by a non-idle signal from usb line (not by an upstream resume). this triggers a usb interrupt when ewupcpu is set in the table on page 119. when receiving this interrupt, user has to enable all usb clock inputs. this bit should be cleared by software (usb clocks must be enabled before). 4eeorint end of reset interrupt this bit is set by hardware when a end of reset has been detected by the usb controller. this triggers a usb interrupt when eeorint is set in the table on page 119. this bit should be cleared by software. 3sofint start of frame interrupt this bit is set by hardware when an usb start of frame pid (sof) has been detected. this triggers a usb interrupt when esofint is set in the table on page 119. this bit should be cleared by software. 2-1 - reserved the value read from these bits is always 0. do not change these bits. 0spint suspend interrupt this bit is set by hardware when a usb suspend (idle bus for three frame periods: a j state for 3 ms) is detected. this triggers a usb interrupt when espint is set in usbien register (table 66 on page 119). this bit must be cleared by software before powering the microcontroller down as it disables the usb pads to reduce the power consumption.
119 at8xc5122/23 4202d?scr?06/05 reset value = 0001 0000b reset value = 1000 0000b table 66. usb global interrupt enable register - usbien (s:beh) 76 5 43210 - - ewupcpu eeorint esofint - - espint bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not change these bits. 5 ewupcpu enable wake-up cpu interrupt set this bit to enable wake-up cpu interrupt. clear this bit to disable wake-up cpu interrupt. 4 eeorint enable end of reset interrupt set this bit to enable end of reset in terrupt. this bit is set after reset. clear this bit to disable end of reset interrupt. 3 esofint enable sof interrupt set this bit to enable sof interrupt. clear this bit to disable sof interrupt. 2-1 - reserved the value read from these bits is always 0. do not change these bits. 0 espint enable suspend interrupt set this bit to enable suspend interrupts (see table 65 on page 118). clear this bit to disable suspend interrupts. table 67. usb address register - usbaddr (s:c6h) 76543210 fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 bit number bit mnemonic description 7fen function enable set this bit to enable the function. fadd is reset to 1. cleared this bit to disable the function. 6-0 uadd[6:0] usb address this field contains the default address (0) after power-up or usb bus reset. it should be written with the value set by a set_address request received by the device firmware.
120 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b reset value = 1000 0000b when uepnum = 0 reset value = 0000 0000b otherwise table 68. usb endpoint number - uepnum (s:c7h) 76543210 ----epnum3epnum2epnum1epnum0 bit number bit mnemonic description 7 - 4 - reserved the value read from these bits is always 0. do not change these bits. 3 - 0 epnum[3:0] endpoint number set this field with the number of the endpoint which should be accessed when reading or writing to, usb byte count register x (x=epnum set in uepnum register) - ubyctx (s:e2h) or usb endpoint x control register - uepconx (s:d4h). this value can be 0, 1, 2, 3, 4, 5 or 6. table 69. usb endpoint x control register - uepconx (s:d4h) 76543210 epen nakien nakout nakin dtgl epdir eptype1 eptype0 bit number bit mnemonic description 7 epen endpoint enable set this bit to enable the endpoint according to the device configuration. endpoint 0 will always be enabled after a hardware or usb bus reset and part icipate in the device configuration. clear this bit to disable the endpoint according to the device configuration. 6 nakien nak interrupt enable set this bit to enable nakin and nakout interrupt. clear this bit to disable nakin and nakout interrupt. 5nakout nak out sent this bit is set by hardware when the a nak handshake is sent by the usb controller to an out request from the host. this generates an interrupt if the nakien bit is set. this bit shall be cleared by software. 4nakin nak in sent this bit is set by hardware when t he a nak handshake is sent by the usb controller to an in request from the host. this generates an interrupt if the nakien bit is set. this bit shall be cleared by software. 3dtgl data toggle (read-only) this bit is set by hardware when a valid data0 packet is received and accepted. this bit is cleared by hardware when a va lid data1 packet is received and accepted. 2 epdir endpoint direction set this bit to configure in direction fo r bulk, interrupt and isochronous endpoints. clear this bit to configure out direction for bulk, interrupt and isochronous endpoints. this bit has no effect for control endpoints. 1-0 eptype[1:0] endpoint type set this field according to the endpoint configurat ion (endpoint 0 will always be configured as control): 00control endpoint 01isochronous endpoint 10bulk endpoint 11interrupt endpoint
121 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 70. usb endpoint status and control register x - uepstax (s:ceh ) x=epnum set in uepnum register) 76543210 dir rxoutb1 stallrq txrdy stl/crc rxsetup rxoutb0 txcmp bit number bit mnemonic description 7dir control endpoint direction this bit is used only if the endpoint is configured in the control type (see?usb endpoint x control register - uepconx (s:d4h)? on page 120). this bit determines the control data and status direction. the device firmware should set this bit only for the in da ta stage, before any other usb operation. otherwise, the device firmware should clear this bit. 6 rxoutb1 received out data bank 1 for endpoint 6 (ping-pong mode) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 1 (only in ping-pong mode). then, the endpoint interrupt is triggered if enabled (see ?usb gl obal interrupt register - usbint (s:bdh)? on page 118) and all the following out packets to the endpoint bank 1 are rejected (nak?ed) until this bit has been cleared, excepted for isochronou s endpoints. this bit should be cleared by the device firmware after reading the out data from the endpoint fifo. 5 stallrq stall handshake request set this bit to request a stall answer to the host for the next handshake. clear this bit otherwise. for control endpoints: cleared by hardware when a valid setup pid is received. 4 txrdy tx packet ready set this bit after a packet has been written into the endpoint fi fo for in data transfers. data should be written into the endp oint fifo only after this bit has been cleared. set this bit without writing data to the endpoint fifo to send a zero length packet. this bit is cleared by hardware, as soon as the packet has been sent for isochronous end points, or after the host has acknowledged the packet for control, bulk and interrupt endpoints. when this bit is cleared, the endpoint interrupt is triggere d if enabled (see table 65 on page 118). 3 stlcrc stall sent / crc error flag - for control, bulk and interrupt endpoints: this bit is set by hardware after a stall handshake has been s ent as requested by stallrq. then, the endpoint interrupt is triggered if enabled (see?? on page 118) it should be cleared by the device firmware. - for isochronous endpoints (read-only) : this bit is set by hardware if the last received data is corrupted (crc error on data). this bit is updated by hardware when a new data is received. 2 rxsetup received setup this bit is set by hardware when a valid setup packet has been re ceived from the host. then, all the other bits of the register are cleared by hardware and the endpoint interrupt is triggered if enabled (see table 65 on page 118). it should be cleared by the device fi rmware after reading the setup data from the endpoint fifo. 1 rxoutb0 received out data bank 0 (see also rxoutb1 bit for ping-pong endpoints) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 0. then, the endpoint interrupt i s triggered if enabled (see?? on page 118) and all the following out packets to the endpoint bank 0 are rejected (nak?ed) until t his bit has been cleared, excepted for isochronous endpoints. howe ver, for control endpoints, an early setup transaction may overwrite the content of the endpoint fifo, even if its data packet is received while this bit is set. this bit should be cleared by the device firmware after reading the out data from the endpoint fifo. 0txcmpl transmitted in data complete this bit is set by hardware after an in packet has been trans mitted for isochronous endpoints and after it has been accepted (ack?ed) by the host for control, bulk and interrupt endpoint s. then, the endpoint interrupt is triggered if enabled (see table 65). this bit should be cleared by the de vice firmware before setting txrdy.
122 at8xc5122/23 4202d?scr?06/05 reset value = xxxx xxxxb reset value = 0000 0000b table 71. usb fifo data endpoint x (x=epn um set in uepnum register) - uepdatx (s:cfh) 76543210 fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 bit number bit mnemonic description 7 - 0 fdat [7:0] endpoint x fifo data data byte to be written to fifo or data byte to be read from the fifo, for the endpoint x (see epnum). table 72. usb byte count register x (x=epnum set in uepnum register) - ubyctx (s:e2h) 76543210 - byct6 byct5 byct4 byct3 byct2 byct1 byct0 bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6 - 0 byct[6:0] byte count lsb least significant byte of the byte count of a received data packet. this byte count is equal to the number of data bytes received after the data pid.
123 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 73. usb endpoint fifo reset register - ueprst (s:d5h) 76543210 - ep6rst ep5rst ep4rst ep3rst ep2rst ep1rst ep0rst bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6 ep6rst endpoint 6 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 5 ep5rst endpoint 5 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 4 ep4rst endpoint 4 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 3 ep3rst endpoint 3 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 2 ep2rst endpoint 2 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 1 ep1rst endpoint 1 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 0 ep0rst endpoint 0 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo.
124 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 74. usb endpoint interrupt register - uepint (s:f8h read-only) 76543210 - ep6int ep5int ep4int ep3int ep2int ep1int ep0int bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6 ep6int endpoint 6 interrupt this bit is set by hardware when an in terrupt has been detected on the endpoint 6. the interrupt sources are part of uepstax register and can be : txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep6inte bit in the uepien register is set. this bit is cleared by hardware when all the interrupt sources are cleared. 5 ep5int endpoint 5 interrupt this bit is set by hardware when an in terrupt has been detected on the endpoint 5. the interrupt sources are part of uepstax register and can be : txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep5inte bit in the uepien register is set. this bit is cleared by hardware when all the interrupt sources are cleared. 4 ep4int endpoint 4 interrupt this bit is set by hardware when an in terrupt has been detected on the endpoint 4. the interrupt sources are part of uepstax register and can be : txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep4inte bit in the uepien register is set. this bit is cleared by hardware when all the interrupt sources are cleared. 3 ep3int endpoint 3 interrupt this bit is set by hardware when an in terrupt has been detected on the endpoint 3. the interrupt sources are part of uepstax register and can be : txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep3inte bit in the uepien register is set. this bit is cleared by hardware when all the interrupt sources are cleared. 2 ep2int endpoint 2 interrupt this bit is set by hardware when an in terrupt has been detected on the endpoint 2. the interrupt sources are part of uepstax register and can be : txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep2inte bit in the uepien register is set. this bit is cleared by hardware when all the interrupt sources are cleared. 1 ep1int endpoint 1 interrupt this bit is set by hardware when an in terrupt has been detected on the endpoint 1. the interrupt sources are part of uepstax register and can be : txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep1inte bit in the uepien register is set. this bit is cleared by hardware when all the interrupt sources are cleared. 0 ep0int endpoint 0 interrupt this bit is set by hardware when an in terrupt has been detected on the endpoint 0. the interrupt sources are part of uepstax register and can be : txcmp, rxoutb0, rxoutb1, rxsetup or stlcrc. a usb interrupt is triggered when the ep0inte bit in the uepien register is set. this bit is cleared by hardware when all the interrupt sources are cleared.
125 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 75. usb endpoint interrupt enable register - uepien (s:c2h) 76543210 - ep6inte ep5inte ep4inte ep3 inte ep2inte ep1inte ep0inte bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6ep6inte endpoint 6 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 5ep5inte endpoint 5 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 4ep4inte endpoint 4 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 3ep3inte endpoint 3 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 2ep2inte endpoint 2 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 1ep1inte endpoint 1 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 0ep0inte endpoint 0 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint.
126 at8xc5122/23 4202d?scr?06/05 serial i/o port the serial i/o port in the at8xc5122/23 is compatible with the serial i/o port in the 80c52. the i/o port provides both synchronous and asynchronous communication modes. it operates as an universal asynchronous rece iver and transmitter (uart) in three full- duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o port includes the following enhancements: ? framing error detection ? automatic address recognition framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error dete ction feature, set smod0 bit in pcon regis- ter (see figure 65). figure 65. framing error block diagram when this feature is enabled, the receiver checks each incoming dat a frame for a valid stop bit. an invalid stop bit ma y result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see figure 70 on page 130) bit is set. software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 66 and figure 67). figure 66. uart timings in mode 1 ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control (smod0 = 0) set fe bit if stop bit is 0 (framing error) (smod0 = 1) scon (98h) pcon (87h) data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1
127 at8xc5122/23 4202d?scr?06/05 figure 67. uart timings in modes 2 and 3 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by al lowing the serial port to examine the address of each incoming command frame. only when the se rial port recognizes its own address, the receiver sets ri bit in scon register to gene rate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and aut omatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains don?t care bits (defined by zeros) to form the device?s given address. the don?t care bits provide the flexibility to address on e or more slaves at a time. the following example illu strates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1100b given0101 01xxb the following is an example of how to use gi ven addresses to address different slaves: slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b given1111 0xx1b slave c:saddr1111 0011b saden 1111 1101b given1111 00x1b ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1
128 at8xc5122/23 4202d?scr?06/05 the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t care bi t; for slaves b and c, bit 0 is a 1. to commu- nicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t care bits, e.g.: saddr0101 0110b saden1111 1100b broadcast =saddr or saden1111 111xb the use of don?t care bits provides flexibilit y in defining the broadc ast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b broadcast1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b broadcast1111 1x11b, slave c:saddr=1111 0010b saden 1111 1101b broadcast1111 1111b for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. reset addresses on reset, the saddr and saden registers ar e initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don?t care bits). th is ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that does not support automatic address recognition. timer 1 when using the timer 1, the baud rate is der ived from the overflow of the timer. as shown in figure 68 the timer 1 is used in its 8-bit auto-reload mode). smod1 bit in pcon register allows doubling of the generated baud rate.
129 at8xc5122/23 4202d?scr?06/05 figure 68. timer 1 baud rate generator block diagram internal baud rate generator when using the internal baud rate generator, the baud rate is derived from the over- flow of the timer. as show n in figure 69 the internal baud rate generator is an 8-bit auto-reload timer feed by the peripheral clo ck or by the peripheral clock divided by 6 depending on the spd bit in bdrcon register (see table 82 on page 136). the internal baud rate generator is enabled by settin g brr bit in bdrcon register. smod1 bit in pcon register allows doubling of the generated baud rate. figure 69. internal baud rate generator block diagram synchronous mode (mode 0) mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the i/0 capabilities of a device with shift registers. the transmit data (txd) pin outputs a set of eight clock pulses while the receive data (rxd) pin transmits or receives a byte of data. the 8-bit data are transmitted and received leas t-significant bit (lsb) first. shifts occur at a fixed baud rate (see section ?baud rate selection (mode 0)?). figure 70 shows the serial port block diagram in mode 0. tr1 tcon.6 0 1 gate1 tmod.7 overflow c/t1# tmod.6 tl1 (8 bits) th1 (8 bits) int1# t1 ck_ t1 / 6 0 1 smod1 pcon.7 / 2 t1 clock to serial port 0 1 overflow spd bdrcon.1 brg (8 bits) brl (8 bits) ck_ si / 6 ibrg clock brr bdrcon.4 0 1 smod1 pcon.7 / 2 to serial port
130 at8xc5122/23 4202d?scr?06/05 figure 70. serial i/o port bl ock diagram (mode 0) transmission (mode 0) to start a transmission mode 0, write to scon register clearing bits sm0, sm1. as shown in figure 71, writing the byte to tran smit to sbuf register starts the transmis- sion. hardware shifts the lsb (d0) onto the rxd pin during the first clock cycle composed of a high level then low level signal on txd. during the eighth clock cycle the msb (d7) is on the rxd pin. then, hardware drives the rxd pin high and asserts ti to indicate the end of the transmission. figure 71. transmission wa veforms (mode 0) reception (mode 0) to start a reception in mode 0, write to scon register clearing sm0, sm1 and ri bits and setting the ren bit. as shown in figure 72, clock is pulsed and the lsb (d0) is sampled on the rxd pin. the d0 bit is then shifted into the shift register. after eight sampling, the msb (d7) is shifted into the shift register, and hardware as serts ri bit to indicate a completed recep- tion. software can then read the received byte from sbuf register. figure 72. reception waveforms (mode 0) ibrg clock txd rxd sbuf tx sr sbuf rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 mode controller ri scon.0 ti scon.1 ck_ t1 baud rate controller write to sbuf txd rxd ti d0 d1 d2 d3 d4 d5 d6 d7 write to scon txd rxd ri d0 d1 d2 d3 d4 d5 d6 d7 set ren, clear ri
131 at8xc5122/23 4202d?scr?06/05 baud rate selection (mode 0) in mode 0, baud rate can be either fixed or variable. as shown in figure 73, the selection is done using m0src bit in bdrcon register. figure 74 gives the baud rate calculation formulas for each baud rate source. figure 73. baud rate source selection (mode 0) figure 74. baud rate formulas (mode 0) asynchronous modes (modes 1, 2 and 3) the serial port has one 8-bit and two 9-bi t asynchronous modes of operation. figure 75 shows the serial port block diag ram in such asynchronous modes. figure 75. serial i/o port block diagram (modes 1, 2 and 3) mode 1 mode 1 is a full-duplex, asynchronous mode. the data frame (see figure 76) consists of 10 bits: one start, eight data bits and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. when a data is received, the stop bit is read in the rb8 bit in scon register. 0 1 m0src bdrcon.0 ck_ si / 6 to serial port ibrg clock baud_rate = 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f ck_si brl = 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f ck_si a. fixed formula b. variable formula baud_rate = 6 f ck_si tb8 scon.3 ibrg clock rxd txd sbuf tx sr rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 ri scon.0 ti scon.1 mode & clock controller sbuf rx rb8 scon.2 sm2 scon.4 t1 clock ck_ si
132 at8xc5122/23 4202d?scr?06/05 figure 76. data frame format (mode 1) modes 2 and 3 modes 2 and 3 are full-duplex, asynchronous modes. the data frame (see figure 77) consists of 11 bits: one star t bit, eight data bits (transmi tted and received lsb first), one programmable ninth data bit and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. on receive, the ninth bit is read from rb8 bit in scon register. on transmit, the ninth data bit is wr itten to tb8 bit in sc on register. alterna- tively, you can use the ninth bit as a command/data flag. figure 77. data frame format (modes 2 and 3) transmission (modes 1, 2 and 3) to initiate a transmission, write to scon register, setting sm0 and sm1 bits according to figure 70 on page 130, and setting the ninth bit by writing to tb8 bit. then, writing the byte to be transmitted to sbuf r egister starts the transmission. reception (modes 1, 2 and 3) to prepare for a reception, write to scon register, setting sm0 and sm1 bits according to figure 70 on page 130, and setting ren bit. the actual reception is then initiated by a detected high-to-low transition on the rxd pin. framing error detection (modes 1, 2 and 3) framing error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register as shown in figure 78. when this feature is enabled, the receiver checks each incoming dat a frame for a valid stop bit. an invalid stop bit ma y result from noise on the serial lines or from simultaneous transmission by two devices. if a valid stop bit is not found, the software sets fe bit in scon register. software may examine fe bit after each reception to check for data errors. once set, only software or a chip reset clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when the framing erro r detection feature is enabled, ri rises on stop bit instead of the last data bi t as detailed in figure 76 and figure 77. figure 78. framing error block diagram mode 1 d0 d1 d2 d3 d4 d5 d6 d7 start bit 8-bit data stop bit modes 2 and 3 d0 d1 d2 d3 d4 d5 d6 d8 start bit 9-bit data stop bit d7 sm0 1 0 smod0 pcon.6 sm0/fe scon.7 framing error controller fe
133 at8xc5122/23 4202d?scr?06/05 baud rate selection (modes 1 and 3) in modes 1 and 3, the baud rate is derived either from the timer 1 or the internal baud rate generator and allows different baud rate in reception and transmission. as shown in figure 79 the selection is do ne using rbck and tbck bits in bdrcon register. figure 80 gives the baud rate calculation formulas for each baud rate source while table 76 details internal baud rate generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. figure 79. baud rate source selection (modes 1 and 3) figure 80. baud rate formulas (modes 1 and 3) 0 1 rbck bdrcon.2 t1 clock to serial ibrg clock reception port 0 1 tbck bdrcon.3 t1 clock to serial ibrg clock transmission port / 16 / 16 baud_rate = 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f ck_si brl = 256 - 6 (1-spd ) ? 32 ? baud_rate 2 smod1 ? f ck_si baud_rate = 6 ? 32 ? (256 -th1) 2 smod1 ? f ck_t1 th1 = 256 - 192 ? baud_rate 2 smod1 ? f ck_t1 a. ibrg formula b. t1 formula
134 at8xc5122/23 4202d?scr?06/05 baud rate selection (mode 2) in mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of the peripheral clock frequency. as shown in figure 81 the selection is done using smod1 bit in pcon register. figure 82 gives the baud rate calculation formula depending on the selection. figure 81. baud rate generator selection (mode 2) figure 82. baud rate formula (mode 2) for mode 0 for uart, thanks to the bit m0 src located in bdrcon register (table 82) table 76. internal baud rate generator value baud rate f ck_idle = 4 mhz f ck_idle = 8 mhz f ck_idle = 9.6 mhz spd smod1 brl error% spd smod1 brl error% spd smod1 brl error% 115200 1 1 254 8.51 1 1 252 8.51 1 1 251 4.17 57600 1 1 252 8.51 1 1 247 3.55 1 1 246 4.17 38400 1 1 249 6.99 1 1 243 0.16 1 1 240 2.34 19200 1 1 243 0.16 1 1 230 0.16 1 1 225 0.81 9600 1 1 230 0.16 1 1 204 0.16 1 1 194 0.81 4800 1 1 204 0.16 1 1 152 0.16 1 1 131 0.00 baud rate f ck_idle = 12 mhz f ck_idle = 16 mhz f ck_idle = 24 mhz spd smod1 brl error% spd smod1 brl error% spd smod1 brl error% 115200 1 1 249 6.99 1 1 247 3.55 1 1 243 0.16 57600 1 1 243 0.16 1 1 239 2.12 1 1 230 0.16 38400 1 1 236 2.34 1 1 230 0.16 1 1 217 0.16 19200 1 1 217 0.16 1 1 204 0.16 1 1 178 0.16 9600 1 1 178 0.16 1 1 152 0.16 1 1 100 0.16 4800 1 1 100 0.16 1 1 48 0.16 1 1 n/a n/a 0 1 smod1 pcon.7 ck_ si / 2 3 16 to serial port baud_rate = 32 2 smod1 ? f ck_si
135 at8xc5122/23 4202d?scr?06/05 registers reset value = 0000 0000b (bit addressable) table 77. serial control register - scon (98h) 76543210 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 in pcon register must be set to enable access to the fe bit sm0 serial port mode bit 0 (smod0=1 ) refer to sm1 for serial port mode selection. smod0 in pcon register must be clea red to enable access to the sm0 bit 6sm1 serial port mode bit 1 sm0 sm1 mode descriptionbaud rate 0 0 0 shift register f ck_idle /6 0 1 1 8-bit uartvariable 102 9-bit uartf ck_idle /32 or /16 1 1 3 9-bit uartvariable 5sm2 serial port mode 2 bit/multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4ren reception enable bit clear to disable serial reception. set to enable serial reception. 3tb8 transmitter bit 8/ninth bit to transmit in modes 2 and 3 clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2rb8 receiver bit 8/ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the re ceived stop bit. in mode 0 rb8 is not used. 1ti transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 66 and figure 67 in the other modes.
136 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b reset value = 0000 0000b reset value = xxxx xxxxb reset value = 0000 0000b table 82. baud rate control regi ster - bdrcon - (9bh) reset value = xxx0 0000b (not bit addressable) table 78. slave address mask register for uart - saden (b9h) 76543210 table 79. slave address register for uart - saddr (a9h) 76543210 table 80. serial buffer register for uart - sbuf (99h) 76543210 table 81. baud rate reload register for the internal baud rate generator, uart - brl (9ah) 76543210 7 6 5 4 3 2 1 0 - - - brr tbck rbck spd m0src bit number bit mnemonic description 7 - 5 - reserved the value read from this bit is i ndeterminate. do not change these bits. 4brr baud rate run control bit cleared to stop the internal baud rate generator. set to start the internal baud rate generator. 3tbck transmission baud rate generator selection bit for uart cleared to select timer 1 for the baud rate generator. set to select internal baud rate generator. 2rbck reception baud rate generator selection bit for uart cleared to select timer 1 for the baud rate generator. set to select internal baud rate generator. 1 spd baud rate speed control bit for uart cleared to select the slow baud rate generator. set to select the fast baud rate generator. 0m0src baud rate source select bit in mode 0 for uart cleared to select f ck_si /6 as the baud rate generator. set to select the internal baud rate generator for uart in mode 0.
137 at8xc5122/23 4202d?scr?06/05 serial port interface (spi) only for at8xc5122. the serial peripheral interface module (spi) which allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. features features of the spi module include the following: ? full-duplex, three-wire synchronous transfers ? master or slave operation ? eight programmable master clock rates ? serial clock with programmable polarity and phase ? master mode fault error flag with mcu interrupt capability ? write collision flag protection signal description figure 83 shows a typical spi bus configur ation using one master controller and many slave peripherals. the bus is made of three wires connecting all the devices: figure 83. typical spi bus the master device selects the individual slav e devices by using four pins of a parallel port to control the four ss pins of the slave devices. master output slave input (mosi) this 1-bit signal is directly connected be tween the master device and a slave device. the mosi line is used to transfer data in se ries from the master to the slave. therefore, it is an output signal from the master, and an input signal to a slave. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. master input slave output (miso) this 1-bit signal is directly connected between the slave device and a master device. the miso line is used to transfer data in se ries from the slave to the master. therefore, it is an output signal from t he slave, and an input signal to the master. a byte (8-bit word) is transmitted mo st significant bit (msb) first, least significant bit (lsb) last. spi serial clock (sck) this signal is used to synchronize the data movement both in and out the devices through their mosi and miso lines. it is dr iven by the master for eight clock cycles which allows to exchange one byte on the serial lines. slave 1 miso mosi sck ss miso mosi sck ss 0 1 2 3 slave 3 slave 4 miso mosi sck ss slave 2 vdd master port miso mosi sck ss miso mosi sck ss
138 at8xc5122/23 4202d?scr?06/05 slave select (ss ) each slave peripheral is selected by one slave select pin (ss ). this signal must stay low for any message for a slave. only one master (ss high level) can drive the network. the master may select each slave device by software through port pins (figure 83). to prevent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. in a master configuration, the ss line can be used in conjun ction with the modf flag in the spi status register (spsta) to prevent multiple masters from driving mosi and sck (see section ?error conditions?, page 142). a high level on the ss pin puts the miso line of a slav e spi in a high-impedance state. the ss pin could be used as a general-purpos e if the following conditions are met: ? the device is configured as a master and the ssdis control bit in spcon is set. this kind of configuration can be found when only one master is driving the network and there is no way that the ss pin will be pulled low. ther efore, the modf flag in the spsta will never be set (1) . ? the device is configured as a slav e with cpha and ssdis control bits set (2) . this kind of configuration can happen when the system comprises one master and one slave only. therefore, the device should a lways be selected and there is no reason that the master uses the ss pin to select the communicating slave device. baud rate in master mode, the baud rate can be selected from a baud rate generator which is con- troled by three bits in the spcon register : spr2, spr1 and spr0. the master clock is chosen from one of six clock ra tes resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. table 83 gives the different clock rates selected by spr2:spr1:spr0 table 83. spi master baud rate selection 1. clearing ssdis control bit does not clear modf. 2. special care should be taken not to set ssdis control bit when cpha = ?0? because in this mode, the ss is used to start the transmission. spr2:spr1:spr0 clock rate baud rate divisor (bd) 000 reserved n/a 001 f ck_spi /4 4 010 f ck_spi / 8 8 011 f ck_spi /16 16 100 f ck_spi /32 32 101 f ck_spi /64 64 110 f ck_spi /128 128 111 reserved n/a
139 at8xc5122/23 4202d?scr?06/05 functional description figure 84 shows a detailed structure of the spi module. figure 84. spi module block diagram operating modes the serial peripheral interface can be configured as one of the two modes: master mode or salve mode. the configuration and initialization of the spi module is made through one register: ? the serial peripheral control register (spcon) once the spi is configured, the data exchange is made using: ? spcon ? the serial peripheral status register (spsta) ? the serial peripheral data register (spdat) during an spi transmission, data is simultane ously transmitted (shifted out serially) and received (shifted in serially). a serial cloc k line (sck) synchronizes shifting and sam- pling on the two serial data lines (mos i and miso). a slave select line (ss ) allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. when the master device transmits data to t he slave device via the mosi line, the slave device responds by sending data to the master device via the miso line. this implies full-duplex transmission with both data out and data in synchronized with the same clock (figure 85). shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic clock divider clock select /4 /64 /128 spi interrupt request 8-bit bus 1-bit signal ss intclk /32 /8 /16 receive data register spdat spi control spsta cpha spr0 spr1 cpol mstr ssdis spen spr2 spcon wcol modf spif - ----
140 at8xc5122/23 4202d?scr?06/05 figure 85. full-duplex master-sla ve interconnection master mode the spi operates in master mode when the master bit, mstr (3) , in the spcon register is set. only one master spi device can initiate transmissions. software begins the trans- mission from a master spi module by writin g to the serial peripheral data register (spdat). if the shift register is empty, th e byte is immediately transferred to the shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck. simultaneously, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the serial pe ripheral transfer data flag, spif, in spsta becomes set. at the same time that spif beco mes set, the received byte from the slave is transferred to the receive data register in spdat. software clears spif by reading the serial peripheral status register (spsta) with the spif bit set, and then reading the spdat. when the pin ss is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the spdat is resent. slave mode the spi operates in slave mode when the master bit, mstr (4) , in the spcon register is cleared. before a data transmission occurs, the slave select pin, ss , of the slave device must be set to ?0?. ss must remain low until th e transmission is complete. in a slave spi module, data enters the shift register under the control of the sck from the master spi module. after a byte enters the shift register, it is immediately transferred to the receive data register in spdat, and the spif bit is set. to prevent an overflow condition, slave software must then read the spdat before another byte enters the shift register (5) . a slave spi must complete the writ e to the spdat (s hift register) at least one bus cycle before the master spi starts a transmission. if the write to the data register is late, the spi transmits the data al ready in the shift register from the previous transmission. transmission formats software can select any of four combinati ons of serial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol (6) ) and the clock phase (cpha (4) ). cpol defines the default sck line leve l in idle state. it has no significant effect on the transmission format. cpha de fines the edges on which the input data are sampled and the edges on which the output data are shifted (figure 86 and figure 87). the clock phase and polarity should be ident ical for the master spi device and the com- municating slave device. 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck vss vdd ss ss slave mcu 3. the spi module should be co nfigured as a master before it is enabled (spen set). also the master spi should be conf igured before the slave spi. 4. the spi module should be configured as a slave before it is enabled (spen set). 5. the maximum frequency of the sck for an spi configured as a slave is the bus clock speed. 6. before writing to the cpol and cpha bits , the spi should be di sabled (spen = ?0?).
141 at8xc5122/23 4202d?scr?06/05 figure 86. data transmission format (cpha = 0) figure 87. data transmission format (cpha = 1) as shown in figure 86, the first sck edge is the msb capture strobe. therefore the slave must begin drivin g its data before the first sck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte transmitted (figure 88). figure 88. cpha/ss timing figure 87 shows an spi transmission in whic h cpha is ?1?. in this case, the master begins driving its mosi pin on the first sck edge. therefore, the slave uses the first sck edge as a start transmission signal. the ss pin can remain low between transmis- msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0)
142 at8xc5122/23 4202d?scr?06/05 sions (figure 88). this format may be preferab le in systems having only one master and only one slave driving the miso data line. error conditions the following flags in the spsta signal spi error conditions. mode fault (modf) modf error bit in master mode spi indicate s that the level on the slave select (ss ) pin is inconsistent with the actual mode of the device. modf is set to warn that there may have a multi-master conflict fo r system control. in this case , the spi system is affected in the following ways: ? an spi receiver/error cpu interrupt request is generated. ? the spen bit in spcon is cl eared. this disable the spi. ? the mstr bit in spcon is cleared. when ss disable (ssdis) bit in the spcon regist er is cleared, the modf flag is set when the ss signal becomes ?0?. however, as stated before, for a system with one master, if the ss pin of the master device is pulled low, there is no way that an other master is attempting to drive the net- work. in this case, to prevent the modf flag from being set, soft ware can set the ssdis bit in the spcon register and therefore making the ss pin as a general-purpose i/o pin. clearing the modf bit is ac complished by a read of spsta register with modf bit set, followed by a write to the spcon register. spen control bit may be re stored to its orig- inal set state after the modf bit has been cleared. write collision (wcol) a write collision (wcol) flag in the spsta is set when a write to the spdat register is done during a transmit sequence. wcol does not cause an interruption, and the transfer continues uninterrupted. clearing the wcol bit is done through a software sequence of an access to spsta and an access to spdat. overrun condition an overrun condition occurs when the master device tries to send several data bytes and the slave device has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the by te sent after the spif bit was last cleared. a read of the spdat return s this byte. all others bytes are lost. this condition is not detected by the spi peripheral. ss error flag ( sserr ) a synchronous serial slave error occurs when ss goes high before the end of a received data in slave mode. sserr does not cause in interr uption, this bit is cleared by writing 0 to spen bit ( rese t of the spi state machine ). interrupts two spi status flags can genera te a cpu interrupt requests: table 84. spi interrupts serial peripheral data transf er flag, spif: this bit is se t by hardware when a transfer has been completed. spif bit generates transmitter cpu interrupt requests. flag request spif (sp data transfer) spi transmitter interrupt request modf (mode fault) spi receiver/error interrupt request (if ssdis = ?0?)
143 at8xc5122/23 4202d?scr?06/05 mode fault flag, modf: this bit becomes se t to indicate that the level on the ss is inconsistent with the mode of the spi. modf with ssdis reset, generates receiver/error cpu interrupt requests. figure 89 gives a logical view of the above statements. figure 89. spi interrupt requests generation registers there are three registers in the module that provide control, status and data storage functions. these registers are describes in the following paragraphs. serial peripheral control register (spcon) the serial peripheral control register does the following: ? selects one of the master clock rates ? configures the spi module as master or slave ? selects serial clock polarity and phase ? enables the spi module ? frees the ss pin for a general-purpose ssdis modf cpu interrupt request spi receiver/error cpu interrupt request spi transmitter spi cpu interrupt request spif
144 at8xc5122/23 4202d?scr?06/05 reset value = 00010100b table 85. serial peripheral control register - spcon (c3h) 76543210 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic r/w mode description 7 spr2 rw serial peripheral rate 2 bit with spr1 and spr0 define the clock rate 6 spen rw serial peripheral enable clear to disable the spi interface (internal reset of the spi) set to enable the spi interface 5 ssdis rw ss disable clear to enable ss in both master and slave modes set to disable ss in both master and slave modes. in slave mode, this bit has no effect if cpha = ?0? 4mstrrw serial peripheral master clear to configure the spi as a slave set to configure the spi as a master 3cpolrw clock polarity clear to have the sck set to ?0? in idle state set to have the sck set to ?1? in idle low 2cpharw clock phase clear to have the data sampled when the spsck leaves the idle state (see cpol) set to have the data sampled when the spsck returns to idle state (see cpol) 1 spr1 rw serial peripheral rate (spr2:spr1:spr0) 000: reserved 001: f ck_spi /4 010: f ck_spi /8 011: f ck_spi /16 0 spr0 rw 100: f ck_spi /32 101: f ck_spi /64 110: f ck_spi /128 111: reserved
145 at8xc5122/23 4202d?scr?06/05 serial peripheral status register (spsta) the serial peripheral status register cont ains flags to signal the following conditions: ? data transfer complete ? write collision ? inconsistent logic level on ss pin (mode fault error) reset value = 00x0xxxxb table 86. serial peripheral status and control register - spsta (c4h) 76543210 spif wcol sserr modf - - - - bit number bit mnemonic r/w mode description 7 spif r serial peripheral data transfer flag clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. 6wcolr write collision flag cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. set by hardware to indicate that a collision has been detected. 5 sserr r synchronous serial slave error flag set by hardware when ss is modified before the end of a received data. cleared by disabling the spi (clearing spen bit in spcon). 4modfr mode fault cleared by hardware to indicate that the ss pin is at appropriate logic level, or has been approv ed by a clearing sequence. set by hardware to indicate that the ss pin is at inappropriate logic level 3 - 0 - rw reserved the value read from this bit is indeterminate. do not change these bits.
146 at8xc5122/23 4202d?scr?06/05 serial peripheral data register (spdat) the serial peripheral data register (table 87) is a read/write buffer for the receive data register. a write to spdat plac es data directly into the shif t register. no transmit buffer is available in this model. a read of the spdat returns the value located in the receive buffer and not the content of the shift register. reset value = xxxx xxxxb table 87. serial peripheral data register - spdat (c5h) 76543210 r7 r6 r5 r4 r3 r2 r1 r0 bit number bit mnemonic description 7-0 r7:0 receive data bits spcon, spsta and spdat registers may be read and written at any time while there is no on-going exchange. however, special care should be taken when writing to them while a transmission is on-going: do not change spr2, spr1 and spr0 do not change cpha and cpol do not change mstr clearing spen would immediately disable the peripheral writing to the spdat will cause an overflow
147 at8xc5122/23 4202d?scr?06/05 timers/counters the at8xc5122d implements two general-pur pose, 16-bit timers/counters. although they are identified as timer 0, timer 1, you can independently configure each to operate in a variety of modes as a timer or as an event counter. when operating as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, a timer/counte r counts negative transitions on an exter- nal pin. after a preset number of counts , the counter issues an interrupt request. the timer registers and associ ated control registers are implemented as addressable special function registers (sfrs). two of the sfrs provide programmable control of the timers as follows: ? timer/counter mode control register (t mod) and timer/counter control register (tcon) control respectively timer 0 and timer 1. the various operating modes of each timer/counter are described below. timer/counter operations for example, a basic operation is timer r egisters thx and tlx (x= 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit (trx) in the tcon register (see table 88 on page 152) turns the timer on by allowing the selected input to incre- ment tlx. when tlx overflows, it incremen ts thx and when thx overflows it sets the timer overflow flag (tfx) in the tcon register. setting the trx does not clear the thx and tlx timer registers. timer registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but the trx bit must be cleared to preset their values, otherwise the behavior of the timer/counter is unpredictable. the c/tx# control bit selects timer operati on or counter operation by selecting the divided-down system clock or th e external pin tx as the so urce for the counted signal. the trx bit must be cleared when changing the operating mode, otherwise the behavior of the timer/counter is unpredictable. for timer operation (c/tx#= 0), the timer register counts the divided-down system clock. the timer register is incremented once every peripheral cycle. exceptions are the timer 2 baud rate and clock- o ut modes in which the timer register is incremented by the system clock divided by two. for counter operation (c/tx#= 1), the timer register counts the negative transitions on the tx external input pin. the external input is sampled during every s5p2 state. the programmer?s guide describes the notation fo r the states in a peripheral cycle. when the sample is high in one cycle and low in th e next one, the counter is incremented. the new count value appears in the register duri ng the next s3p1 state after the transition has been detected. since it ta kes 12 states (24 os cillator periods) to recognize a nega- tive transition, the maximum count rate is 1/24 of the os cillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full periph- eral cycle. timer 0 timer 0 functions as either a timer or an event counter in four operating modes. figure 90 through figure 96 show the logic configuration of each mode. timer 0 is controlled by the four lower bits of the tmod register (see table 89 on page 153) and bits 0, 1, 4 and 5 of the tcon register (see table 88 on page 152). the tmod register selects the method of timer gating (gate0), timer or counter operation (t/c0#) and the operating mode (m10 and m00). the tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and inter- rupt type control bit (it0).
148 at8xc5122/23 4202d?scr?06/05 for normal timer operation (gate0= 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0# to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets the tf0 flag and generates an interrupt request. it is important to stop the timer/counter before changing modes. mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (th0 reg- ister) with a modulo-32 prescale r implemented with the lower fi ve bits of the tl0 register (see figure 90). the upper three bits of the tl0 register are indeterminate and should be ignored. prescaler overflow increments the th0 register. figure 91 gives the overflow period calculation formula. figure 90. timer/counter x (x= 0 or 1) in mode 0 figure 91. mode 0 overflow period formula mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with the th0 and tl0 registers connected in a cascade (see figure 92). the selected input increments the tl0 register. figure 93 gives the overflow period ca lculation formula when in timer mode. trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (5 bits) thx (8 bits) intx# tx fck_tx /6 6 ? (16384 ? (thx, tlx)) tfx per = f ck_tx
149 at8xc5122/23 4202d?scr?06/05 figure 92. timer/counter x (x = 0 or 1) in mode 1 figure 93. mode 1 overflow period formula mode 2 (8-bit timer with auto- reload) mode 2 configures timer 0 as an 8-bit time r (tl0 register) that automatically reloads from the th0 register (see figure 94). tl0 ov erflow sets the tf0 flag in the tcon reg- ister and reloads tl0 with the contents of th0, which is preset by the software. when the interrupt request is serviced, the hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to the th0 register. figure 95 gives the autoreload period calculation formula when in timer mode. figure 94. timer/counter x (x = 0 or 1) in mode 2 figure 95. mode 2 autoreload period formula trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx fck_tx /6 6 ? (65536 ? (thx, tlx)) tfx per = f ck_tx trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx fck_tx /6 tfx per = f ck_tx 6 ? (256 ? thx)
150 at8xc5122/23 4202d?scr?06/05 mode 3 (two 8-bit timers) mode 3 configures timer 0 so that registers tl0 and th0 operate as 8-bit timers (see figure 96). this mode is provided for applic ations requiring an addi tional 8-bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in the tmod register, and tr0 and tf0 in the tcon register in the normal manner. th0 is locked into a timer function (counting f uart ) and takes over use of the timer 1 interrupt (tf1) and run con- trol (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. figure 97 gives the autoreload period calculation formulas for both tf0 and tf1 flags. figure 96. timer/counter 0 in mode 3: two 8-bit counters figure 97. mode 3 overflow period formula timer 1 timer 1 is identical to timer 0 except for mode 3 which is a hold-count mode. the fol- lowing comments help to understand the differences: ? timer 1 functions as either a timer or an event counter in three operating modes. figure 90 through figure 94 show the logical configuration for modes 0, 1, and 2. mode 3 of timer 1 is a hold-count mode. ? timer 1 is controlled by the four high-order bits of the tmod register (see table 89 on page 153) and bits 2, 3, 6 and 7 of the tcon register (see table 88 on page 152). the tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and the operating mode (m11 and m01). the tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and the interrupt type control bit (it1). ? timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. ? for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr 1 allows external pin int1# to control timer operation. ? timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag and generates an interrupt request. tr0 tcon.4 tf0 tcon.5 int0# 0 1 gate0 tmod.3 overflow timer 0 interrupt request c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrupt request t0 fck_t0 /6 fck_t0 /6 tf0 per = f ck_t0 6 ? (256 ? tl0) tf1 per = f ck_t0 6 ? (256 ? th0)
151 at8xc5122/23 4202d?scr?06/05 ? when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. ? it is important to stop the timer/counter before changing modes. mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, which is set up as an 8-bit timer (th1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 90). the upper 3 bits of tl1 regist er are ignored. prescaler overflow incre- ments the th1 register. mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer with th1 and tl1 registers connected in cascade (see figure 92). the selected input increments the tl1 register. mode 2 (8-bit timer with auto- reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from the th1 register on overflow (see figure 94). tl1 overflow sets the tf1 flag in the tcon register and reloads tl1 with the contents of th1, which is preset by the soft- ware. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when the tr1 run control bit is not available i.e. when timer 0 is in mode 3.
152 at8xc5122/23 4202d?scr?06/05 registers timer/counter control register reset value = 0000 0000b table 88. tcon (s:88h) 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by the hardware when processor vectors interrupt routine. set by the hardware when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5tf0 timer 0 overflow flag cleared by the hardware when processor vectors interrupt routine or by software when the interrupt is disabled set by the hardware when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it1). set by the hardware when external interrupt is detected on the int1# pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1#). set to select falling edge active ( edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it0). set by the hardware when external interrupt is detected on int0# pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0#). set to select falling edge active ( edge triggered) for external interrupt 0.
153 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 89. timer/counter mode control register - tmod (s:89h) 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int 1# pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m 01 o perating mode 0 0 mode 0:8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1:16-bit timer/counter. 1 0 mode 2:8-bit auto-reload timer/counter (tl1). reloaded from th1 at overflow. 1 1 mode 3:timer 1 halted. retains count. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0# pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0:8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1:16-bit timer/counter. 1 0 mode 2:8-bit auto-reload timer/counter (tl0). reloaded from th0 at overflow. 1 1 mode 3:tl0 is an 8-bit timer/counter. th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits. 0m00
154 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 90. timer 0 high byte register - th0 (s:8ch) 76543210 bit number bit mnemonic description 7:0 high byte of timer 0 table 91. timer 0 low byte register - tl0 (s:8ah) 76543210 bit number bit mnemonic description 7:0 low byte of timer 0 table 92. timer 1 high byte register - th1 (s:8dh) 76543210 bit number bit mnemonic description 7:0 high byte of timer 1 table 93. timer 1 low byte register - tl1 (s:8bh) 76543210 bit number bit mnemonic description 7:0 low byte of timer 1
155 at8xc5122/23 4202d?scr?06/05 keyboard interface only for at8xc5122. introduction the at8xc5122/23 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. it is based on 8 inputs wi th programmable interrupt capability on both high or low level. these inputs are available as alternate function of p5 and allow to exit from idle and power-down modes. description the keyboard interfaces with the c51 core through 3 special function registers: kbls, the keyboard level selection register (table 96 on page 158), kbe, the keyboard interrupt enable register (table 95 on page 157), and kbf, the keyboard flag register (table ). interrupt the keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. an interrupt enable bit ( kbd in ie1) allows global enable or dis- able of the keyboard interrupt (see figure 98). as detailed in figure 99 each keyboard input has the capability to detect a progra mmable level according to kbls.x bit value. level detection is then reported in interrupt flags kbf.x that can be masked by software using kbe.x bits. this structure allows keyboard arrangement from 1 by n to 8 by n matrix and allows usage of p5 inputs for other purpose. the kbf.x flags are set by hardware when an active level is on input p5.x. they are automatically reset after any read access on kbf. if the content of kbf must be ana- lyzed, the first read instruction must tran sfer kbf contend to another location. the kbf register cannot be written by software. figure 98. keyboard interface block diagram figure 99. keyboard input circuitry p5.0 keyboard interface interrupt request ekb ien1.0 input circuitry p5.1 input circuitry p5.2 input circuitry p5.3 input circuitry p5.4 input circuitry p5.5 input circuitry p5.6 input circuitry p5.7 input circuitry kbdit p5.x kbe.x kbf.x kbls.x 0 1
156 at8xc5122/23 4202d?scr?06/05 power reduction mode p5 inputs allow exit from idle and power- down modes as detailed in section "power- down mode". registers reset value = 0000 0000b table 94. keyboard flag register - kbf (9eh) 76543210 kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 bit number bit mnemonic description 7 kbf7 keyboard line 7 flag set by hardware when the port line 7 detects a programmed level. it generates a keyboard interrupt request if the kbe.7 bit in kbe register is set. cleared by hardware after the read of the kbf register. 6 kbf6 keyboard line 6 flag set by hardware when the port line 6 detects a programmed level. it generates a keyboard interrupt request if the kbe.6 bit in kbe register is set. cleared by hardware after the read of the kbf register. 5 kbf5 keyboard line 5 flag set by hardware when the port line 5 detects a programmed level. it generates a keyboard interrupt request if the kbe.5 bit in kbe register is set. cleared by hardware after the read of the kbf register. 4 kbf4 keyboard line 4 flag set by hardware when the port line 4 detects a programmed level. it generates a keyboard interrupt request if the kbe.4 bit in kbe register is set. cleared by hardware after the read of the kbf register. 3 kbf3 keyboard line 3 flag set by hardware when the port line 3 detects a programmed level. it generates a keyboard interrupt request if the kbe.3 bit in kbe register is set. cleared by hardware after the read of the kbf register. 2 kbf2 keyboard line 2 flag set by hardware when the port line 2 detects a programmed level. it generates a keyboard interrupt request if the kbe.2 bit in kbe register is set. cleared by hardware after the read of the kbf register. 1 kbf1 keyboard line 1 flag set by hardware when the port line 1 detects a programmed level. it generates a keyboard interrupt request if the kbe.1 bit in kbe register is set. cleared by hardware after the read of the kbf register. 0 kbf0 keyboard line 0 flag set by hardware when the port line 0 detects a programmed level. it generates a keyboard interrupt request if the kbe.0 bit in kbe register is set. cleared by hardware after the read of the kbf register.
157 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 95. keyboard input enable register - kbe (9dh) 76543210 kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 bit number bit mnemonic description 7 kbe7 keyboard line 7 enable bit cleared to enable standard i/o pin. set to enable kbf.7 bit in kbf register to generate an interrupt request. 6 kbe6 keyboard line 6 enable bit cleared to enable standard i/o pin. set to enable kbf.6 bit in kbf register to generate an interrupt request. 5 kbe5 keyboard line 5 enable bit cleared to enable standard i/o pin. set to enable kbf.5 bit in kbf register to generate an interrupt request. 4 kbe4 keyboard line 4 enable bit cleared to enable standard i/o pin. set to enable kbf.4 bit in kbf register to generate an interrupt request. 3 kbe3 keyboard line 3 enable bit cleared to enable standard i/o pin. set to enable kbf.3 bit in kbf register to generate an interrupt request. 2 kbe2 keyboard line 2 enable bit cleared to enable standard i/o pin. set to enable kbf.2 bit in kbf register to generate an interrupt request. 1 kbe1 keyboard line 1 enable bit cleared to enable standard i/o pin. set to enable kbf.1 bit in kbf register to generate an interrupt request. 0 kbe0 keyboard line 0 enable bit cleared to enable standard i/o pin. set to enable kbf.0 bit in kbf register to generate an interrupt request.
158 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 96. keyboard level selector register - kbls (9ch) 76543210 kbls7 kbls6 kbls5 kbls4 kbls3 kbls2 kbls1 kbls0 bit number bit mnemonic description 7 kbls7 keyboard line 7 level selection bit cleared to enable a low level detection on port line 7. set to enable a high level detection on port line 7. 6 kbls6 keyboard line 6 level selection bit cleared to enable a low level detection on port line 6. set to enable a high level detection on port line 6. 5 kbls5 keyboard line 5 level selection bit cleared to enable a low level detection on port line 5. set to enable a high level detection on port line 5. 4 kbls4 keyboard line 4 level selection bit cleared to enable a low level detection on port line 4. set to enable a high level detection on port line 4. 3 kbls3 keyboard line 3 level selection bit cleared to enable a low level detection on port line 3. set to enable a high level detection on port line 3. 2 kbls2 keyboard line 2 level selection bit cleared to enable a low level detection on port line 2. set to enable a high level detection on port line 2. 1 kbls1 keyboard line 1 level selection bit cleared to enable a low level detection on port line 1. set to enable a high level detection on port line 1. 0 kbls0 keyboard line 0 level selection bit cleared to enable a low level detection on port line 0. set to enable a high level detection on port line 0.
159 at8xc5122/23 4202d?scr?06/05 interrupt system introduction the at8xc5122/23 implements an interrupt controller with 15 inputs but only 9 are used for : ? two external interrupts (int0 and int1 ) ? two timer interrupts (timers 0, 1), ? the uart interface ? the spi interface ? the keyboard interface ? the usb interface ? the smart card interface. interrupt system description each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable regi sters (table 98 on page 162 and table 99 on page 163). these registers also contain a global di sable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one out of four priority lev- els by setting or clearing a bit in the inte rrupt priority low registers (table 101 on page 164 and table 103 on page 166) and in the interrupt priority high register (table 102 on page 165 and table 105 on page 168) shows t he bit values and priority levels associ- ated with each combination. a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt can?t be interrupted by any other interrupt source. if two interrupt requests of different prio rity levels are rece ived simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced first. thus within each priority leve l there is a second priority structure deter- mined by the polling sequence. table 97. priority level bit values iph.x ipl.x interrupt level priority 0 0 0 (lowest) 011 102 1 1 3 (highest)
160 at8xc5122/23 4202d?scr?06/05 figure 100. interrupt control system ie0 spi smart card int1 cpres rxd rxen 0 1 ie1 1 0 0 1 presit isel.0 isel.4 rxit oeen isel.2 oelev isel.3 it1 tcon.2 tcon.3 presen isel.1 cplev isel.7 isel.5 0 1 it0 tcon.0 tf0 tf1 ri ti et1 ien0.3 eusb ien1.6 es ien0.4 ex0 ien0.0 00 01 10 11 ea ien0.7 et0 ien0.1 ex1 ien0.2 ekb (1) ien1.0 espi (1) ien1.2 iph/l interrupt enable lowest priority priority enable 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 esci ien1.3 00 01 10 11 highest priority interrupts interrupts tcon.1 int0# rxd txd d+ d- cio cclk mosi sck miso tcon.5 tcon.7 scon.0 scon.1 p5.x 0 1 kbfx kbex kblsx serial interface controller controller usb controller controller interface note (1) : not applicable to at83c5123 (1)
161 at8xc5122/23 4202d?scr?06/05 i nt1 interrupt vector the int1 interrupt is mult iplexed with the fo llowing three inputs: ? int1 : standard 8051 interrupt input ? rxd : received data on uart ? cpres: insertion or remove of the main card the setting configurations for each input is detailed below. int1 input this interrupt input is active under the following conditions : ? it must be enabled by oeen bit (isel register) ? it can be active on a level or falling ed ge following it1 bit (t con register) status ? if level triggering selection is set, the active level 0 or 1 can be selected with oelev bit (isel register) the bit ie1 (tcon register) is set by hardwa re when external interrupt detected. it is cleared when interrupt is processed. rxd input a second vector interr upt input is the reception of a ch aracter. uart rx input can gen- erate an interrupt if enabled with bit rxen (isel.0). the global enable bits ex1 and ea must also be set. then, the bit rxit (isel register) is set by hardware when a low level is detected on p3.0/rxd input. cpres input the third input is the detection of a level change on cpres input (p1.2). this input can generate an interrupt if en abled with presen (isel.1) , ex1 (ie0.2) and ea (ie0.7) bits. this detection is done according to th e level selected with bit cplev (isel.7). then the bit presit (isel .5) is set by hardware when the triggering conditions are met. this bit must be cleared by software.
162 at8xc5122/23 4202d?scr?06/05 registers reset value = 0000 0000b (bit addressable) table 98. interrupt enable register 0 - ien0 (a8h) 76543210 ea - - es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit cleared to disable all interrupts. set to enable all interrupts. 6 - 5 - reserved the value read from this bit is in determinate. do not change these bits. 4es serial port enable bit cleared to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit cleared to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2 ex1 external interrupt 1 enable bit cleared to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit cleared to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0 ex0 external interrupt 0 enable bit cleared to disable external interrupt 0. set to enable external interrupt 0.
163 at8xc5122/23 4202d?scr?06/05 reset value = x0xx 00x0b (bit addressable) table 99. interrupt enable register 1 - ien1 (b1h) for at8xc5122 76543210 - eusb - - esci espi - ekb bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6eusb usb interrupt enable bit cleared to disable usb interrupt . set to enable usb interrupt. 5 - 4 - reserved the value read from this bit is indet erminate. do not change these bits. 3 esci sci interrupt enable bit cleared to disable sciinterrupt . set to enable sci interrupt. 2 espi spi interrupt enable bit cleared to disable spi interrupt . set to enable spi interrupt. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0 ekb keyboard interrupt enable bit cleared to disable keyboard interrupt . set to enable keyboard interrupt.
164 at8xc5122/23 4202d?scr?06/05 reset value = x0xx 0xxxb (bit addressable) reset value = x000 0000b (bit addressable) table 100. interrupt enable register 1 - ien1 (b1h) for at83c5123 76543210 - eusb - - esci - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6eusb usb interrupt enable bit cleared to disable usb interrupt . set to enable usb interrupt. 5 - 4 - reserved the value read from this bit is indet erminate. do not change these bits. 3 esci sci interrupt enable bit cleared to disable sciinterrupt . set to enable sci interrupt. 2 reserved the value read from this bit is indeterminate. do not change this bit. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0 reserved the value read from this bit is indeterminate. do not change this bit. table 101. interrupt priority low re gister 0 - ipl0 (b8h) 76543210 - - - psl pt1l px1l pt0l px0l bit number bit mnemonic description 7 - 5 - reserved the value read from this bit is indet erminate. do not change these bits. 4 psl serial port priority bit refer to psh for priority level. 3pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2 px1l external interrupt 1 priority bit refer to px1h for priority level. 1pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0 px0l external interrupt 0 priority bit refer to px0h for priority level.
165 at8xc5122/23 4202d?scr?06/05 reset value = x000 0000b (not bit addressable) table 102. interrupt priority high register 0 - iph0 (b7h) 76543210 - - - psh pt1h px1h pt0h px0h bit number bit mnemonic description 7 - 5 - reserved the value read from this bit is in determinate. do not change these bits. 4 psh serial port priority high bit ps h psl priority level 0 0 lowest 01 10 1 1 highest 3pt1h timer 1 overflow interrupt priority high bit pt1h p t1l priority level 0 0 lowest 01 10 1 1 highest 2 px1h external interrupt 1 priority high bit p x1h p x1l priority level 0 0 lowest 01 10 1 1 highest 1pt0h timer 0 overflow interrupt priority high bit p t0h pt0l priority level 0 0 lowest 01 10 1 1 highest 0 px0h external interrupt 0 priority high bit px0h p x0l priority level 0 0 lowest 01 10 1 1 highest
166 at8xc5122/23 4202d?scr?06/05 reset value = x00x 00x0b (bit addressable) table 103. interrupt priority low register 1 - ipl1 (b2h) for at8xc5122 76543210 - pusbl - - pscil pspil - pkbdl bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not change this bit. 6 pusbl usb interrupt priority bit refer to pusbh for priority level. 5 - 4 - reserved the value read from this bit is indet erminate. do not change these bits. 3pscil sci interrupt priority bit refer to pspih for priority level. 2 pspil spi interrupt priority bit refer to pspih for priority level. 1- reserved the value read from this bit is i ndeterminate. do not change this bit. 0 pkbl keyboard interrupt priority bit refer to pkbdh for priority level.
167 at8xc5122/23 4202d?scr?06/05 reset value = x0xx 0xxxb (bit addressable) table 104. interrupt priority low register 1 - ipl1 (b2h) for at83c5123 76543210 - pusbl - - pscil bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not change this bit. 6 pusbl usb interrupt priority bit refer to pusbh for priority level. 5 - 4 - reserved the value read from this bit is indet erminate. do not change these bits. 3pscil sci interrupt priority bit refer to pspih for priority level. 2 reserved the value read from this bit is i ndeterminate. do not change this bit. 1 reserved the value read from this bit is i ndeterminate. do not change this bit. 0 reserved the value read from this bit is i ndeterminate. do not change this bit.
168 at8xc5122/23 4202d?scr?06/05 reset value = xxxx x000b (not bit addressable) table 105. interrupt priority high register 1 - iph1 (b3h) for at8xc5122 76543210 - pusbh - - pscih - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6 pusbh usb interrupt priotity high bit p usbh p usbl priority level 00 lowest 01 10 1 1 highest 5-4 - reserved the value read from this bit is i ndeterminate. do not change these bits. 3 pscih sci interrupt priority high bit pscih pscil priority level 00 lowest 01 10 1 1 highest 2 pspih spi interrupt priority high bit pspih pspil priority level 00 lowest 01 10 1 1 highest 1- reserved the value read from this bit is indeterminate. do not change this bit. 0 pkbh keyboard interrupt priority high bit pkbdh pkbdl priority level 00 lowest 01 10 1 1 highest
169 at8xc5122/23 4202d?scr?06/05 reset value = x0xx 0xxxb (not bit addressable) table 106. interrupt priority high register 1 - iph1 (b3h) for at83c5123 76543210 - pusbh - - pscih - - - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6 pusbh usb interrupt priotity high bit pusbh pusbl priority level 00 lowest 01 10 1 1 highest 5-4 - reserved the value read from this bit is i ndeterminate. do not change these bits. 3 pscih sci interrupt priority high bit pscih pscil priority level 00 lowest 01 10 1 1 highest 2 reserved the value read from this bit is i ndeterminate. do not change these bits. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0 reserved the value read from this bit is i ndeterminate. do not change these bits.
170 at8xc5122/23 4202d?scr?06/05 reset value = 0000 0000b table 107. interrupt enable regist er - isel (s:a1h) 76543210 cplev - presit rxit oelev oeen presen rxen bit number bit mnemonic description 7 cplev card presence detection level this bit indicates which cpres level will bring about an interrupt set this bit to indicate that card presence it will appear if cpres is at high level. clear this bit to indicate that card pr esence it will appear if cpres is at low level. 6- reserved the value read from this bit is indeterminate. do not change this bit. 5 presit card presence detection interrupt flag set by hardware must be cleared by software 4 rxit received data interrupt flag set by hardware must be cleared by software 3 oelev int1 signal active level set this bit to indicate that high level is active. clear this bit to indicate that low level is active. 2 oeen int1 interrupt disable bit clear to disable int1 interrupt set to enable int1 interrupt 1 presen card presence detection interrupt enable bit clear to disable the card presence det ection interrupt coming from scib. set to enable the card presence detection interrupt coming from scib. 0 rxen received data interrupt enable bit clear to disable the rxd interrupt. set to enable the rxd interrupt (a minimal bit width of 100 s is required to wake up from power-down) .
171 at8xc5122/23 4202d?scr?06/05 interrupt sources and vectors note: 1. only fot at8xc5122 table 108. interrupt vectors interrupt source polling priority at same level vector address reset 0 (highest priority) c:0000h int0 1 c:0003h timer 0 2 c:000bh int1 3 c:0013h timer 1 4 c:001bh uart 6 c:0023h reserved 7c:002bh reserved 5 c:0033h keyboard controller (1) 8c:003bh reserved 9 c:0043h spi controller (1) 10 c:004bh smart card controller 11 c:0053h reserved 12 c:005bh reserved 13 c:0063h usb controller 14 c:006bh reserved 15 (lowest priority) c:0073h
172 at8xc5122/23 4202d?scr?06/05 microcontroller reset introduction the internal reset is used to start up (cold reset) or to re-start (warm reset) the micro- controller activity. when the reset is appli ed (active state), all internal registers are initialized so that the microcontroller starts from a known and clean state for the program always runs as expected. the reset is released (inactive state) when the following conditions are internally met : ? the power supply has reatched a mini mum level which garantees that the microcontroller works properly ? the on-chip oscillator has reached a minimum oscillation level which ensures a good noise to signal rati o and a correct internal duty cycle ? the active state duration is at least two machine cycles. if one of the above conditions is not met the microcontroller is not correctly reset and might not work properly. the internal reset comes from four different sources : ? reset pin ? power on reset (por) ? power fail detector (pfd) ? hardware watch-dog timer (wdt) figure 101. reset bock diagram watch dog rst internal reset timer microcontroller vcc 3.3v internal digital regulator c51 core vcore por pfd
173 at8xc5122/23 4202d?scr?06/05 power on reset (por) the role of the por is to monitor the power supply rise of the microcontroller core and release the internal reset only when the in ternal voltage exceeds the vpfdp threshold from which the microcontroller core is stable (see figure 102). this feature replaces the external reset function and therefore avoid the use of external components on the reset pin. power fail detector (pfd) the role of the pfd is to monitor the powe r supply falls during a steady state condition in order to suspend the microcontroller and peripherals activity as soon as the power supply drops below the vpfdm threshold from which the microcontroller?s core might become instable (see figure 102). the pdf su spends the microcontroller?s activity by holding the microcontroller under a reset state to avoid an unpredictable behaviour. a filter prevents the system from reseting when glitches lower than 50 ns duration are carried on vcore. see figure 102 and figure 103 on page 174.
174 at8xc5122/23 4202d?scr?06/05 figure 102. static behaviour of por and pfd figure 103. dynamic behaviour of por and pfd vcore t internal vpfdp vpfdm 1 0 por por pfd reset vcore t internal vpfdp vpfdm 1 0 por por pfd reset t<50ns t>50ns
175 at8xc5122/23 4202d?scr?06/05 reset pin as explained in the por section there is no need to use the reset pin as the internal reset function at power up is ensured by the por. anyway, if some applications requires a long reset, a reset controlled by the user or a reset controlled by external superviser device, the use of the reset pin is necessary. long reset as the pad integrates an internal pull-up of 10k, only an external capacitor of at least 10 f is required to have an impact on the reset duration. figure 104. long reset reset controlled by the user the external capacitor is not needed if no long reset is required. figure 105. reset controlled by the user rst vcc 10 k internal reset microcontrolleur 10 f rst vcc 10 k internal reset microcontrolleur
176 at8xc5122/23 4202d?scr?06/05 reset controlled by an external superviser device as the reset pin can be forced in output by the watch-dog timer (wdt) or the por/pfd features, there can be a conflict between the external superviser device and the micro- controller?s reset pin when in one side the ex ternal superviser is pulling the reset pin to vcc and in another side the wdt or por/pfd f eatures tries to force the reset pin to ground. therefore, it recommended to insert a series resistor of 1.8k +/-10% or a diode (1n4148 for instance) between the external superviser device and the reset pin as detailed in the following figures. figure 106. use of an external serial resistor figure 107. use of an external diode rst vcc 10 k microcontrolleur 1.8 k superviser device to other on-board circuitry power fail detector watchdog timer power on reset rst vcc 10 k microcontrolleur superviser device to other on-board circuitry power fail detector watchdog timer power on reset 1n4148
177 at8xc5122/23 4202d?scr?06/05 watchdog timer the at8xc5122/23 microcontrollers contain a powerfull programmable hardware watchdog timer (wdt) that automatically resets the chip if its softwa re fails to reset the wdt before the selected time interval has elapsed. it permits large timeout ranking from 4ms to 524ms @ f ck_wd = 24 mhz / x2 this wdt consist of a 14-bit counter plus a 7-bit programmable counter, a watchdog timer reset register (wdtrst) and a watchdog timer programmation (wdtprg) reg- ister. when exiting the reset, the wdt is, by default, disabled. to activate the wdt, the user has to write the sequence 1eh and e1 h into wdrst register. when the watchdog timer is enabled, it will increment every mach ine cycle while the o scillator is running and there is no way to disable the wdt exc ept through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse duration is 96xt osc , where t osc =1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time requ ired to prevent a wdt reset. the wdt is controlled by two registers (wdtrst and wdtprg). figure 108. watchdog timer reset decoder control wdtrst wr enable 14-bit counter 7 - bit counter outputs f ck_wd reset - - - - - 2 1 0 wdtprg
178 at8xc5122/23 4202d?scr?06/05 reset value = xxxx x000b the three lower bits (s0, s1, s2) located into wdtprg register enables to program the wdt duration. to compute wd timeout, the following formula must be applied: time out = 6 * (2 14 * 2 svalue - 1 ) / f ck_wd note: svalue represents the decimal value of (s2 s1 s0) table 109. watchdog timer out register - wdtprg (0a7h) 76543210 -----s2s1s0 bit number bit mnemonic description 7 - 3 - reserved the value read from this bit is inde terminate. do not change these bits. 2 s2 wdt time-out select bit 2 1 s1 wdt time-out select bit 1 0 s0 wdt time-out select bit 0 table 110. machine cycle count s2 s1 s0 machine cycle count 000 2 14 - 1 001 2 15 - 1 010 2 16 - 1 011 2 17 - 1 100 2 18 - 1 101 2 19 - 1 110 2 20 - 1 111 2 21 - 1
179 at8xc5122/23 4202d?scr?06/05 table 111. timeout value for f ck_wd = 24 mhz / x2 reset value = xxxx xxxxb the wdtrst register is used to reset / enable the wdt by writing 1eh then e1h in sequence. s2 s1 s0 timeout for f ck_wd = 24 mhz / x2 0 0 0 4.10 ms 0 0 1 8.19 ms 0 1 0 16.38 ms 0 1 1 32.77 ms 1 0 0 65.54 ms 1 0 1 131.07 ms 1 1 0 262.14 ms 1 1 1 524.29 ms table 112. watchdog timer enable register (write only) - wdtrst (a6h) 76543210 --------
180 at8xc5122/23 4202d?scr?06/05 power management before activating the idle mode or power down mode, th e cpu clock must be switched to on-chip oscillator source if the pll is used to fed the cpu clock. idle mode an instruction that sets pcon.0 indicates th at it is the last instruction to be executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high level. there are two ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, te rminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one fol- lowing the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occured dur- ing normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator per iods) to comple te the reset. power down mode to save maximum power, a power-down mode can be invoked by software (see table 13, pcon register). warning: to minimize power consumption, all pe ripherals and i/os with static current consumption must be set in the proper st ate. i/os programmed with low speed output configuration (kb_out) must be switch to push-pull or standard c51 configuration before entering power-down. the cvcc generator must also be switch off. in power-down mode, the oscillator is st opped and the instruction that invoked power- down mode is the last instruction executed . the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power- down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillato r to restart and stabilize. only external interrupts int0 , int1 , keyboard, card insertion/removal and usb inter- rupts are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. when keyboard interrupt occurs after a power-down mode, 1024 clocks are nec essary to exit to power-down mode and enter in operating mode. holding the pin low restarts the oscillator bu t bringing the pin high completes the exit as detailed in figure 109. when both interr upts are enabled, the osc illator restarts as soon as one of the two inpu ts is held low and power-down exit will be completed when the first input is released. in this case, the higher priority interrupt service routine is executed. once the interrupt is serviced, the next instru ction to be executed after reti will be the one following the instruction that put at8xc5122/23 into power-down mode.
181 at8xc5122/23 4202d?scr?06/05 figure 109. power-down ex it waveform exit from power-down by rese t redefines all the sfrs, exit from power-down by external interrupt does no affect the sfrs. exit from power-down by either reset or exte rnal interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. table shows the state of ports during idle and power-down modes. note: 1. port 0 can force a 0 level. a "one" will leave port floating. reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit location 0. as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase table state of ports mode program memory ale psen p0 p1 p2 p3 p4 p5 idle internal 1 1 port data (1) port data port data port data port data port data idle external 1 1 floating port data address port data port data port data power-down internal 0 0 port dat* port data port data port data port data port data power-down external 0 0 floating port data port data port data port data port data
182 at8xc5122/23 4202d?scr?06/05 usb interface suspend the suspend state can be dete cted by the usb controller if all the clocks are enabled and if the usb controller is enabled. the bit spint is set by hardware when an idle state is detected for more than 3 ms. this triggers a usb interrupt if enabled. in order to reduce current consumption, th e firmware can put the usb pad in idle mode, stop the clocks and put the c51 in idle or power-down mode. the resume detection is still active. the usb pad is put in idle mode when the firmware clear the spint bit. in order to avoid a new suspend detection 3ms later, t he firmware has to disable the usb clock input using the suspclk bit in the usbcon register. the usb pad automatically exits of idle mode when a wake-up event is detected. the stop of the 48 mhz clock from the pll should be done in the following order: 1. disable of the 48 mhz clock input of th e usb controller by setting to 1 the sus- pclk bit in the usbcon register. 2. if cpu clock is fed from pll, the on-chi p oscillator must be selected to fed the cpu clock. 3. disable the pll by clearing the pllen bit in the pllcon register. resume when the usb controller is in suspend state, the resume detection is active even if all the clocks are disabled and if the c51 is in idle or power-down mode. the wupcpu bit is set by hardware when a non-idle state occurs on the usb bus. this triggers an inter- rupt if enabled. this interrupt wakes up the cpu from its idle or power-down state and the interrupt function is th en executed. the firmware will first enable th e 48 mhz gener- ation and then reset to 0 the suspclk bit in the usbcon register if needed. the firmware has to clear the spint bit in the usbint register before any other usb operation in order to wake up the usb controller from its suspend mode. the usb controller is then re-activated.
183 at8xc5122/23 4202d?scr?06/05 figure 110. example of a suspend/resume management smart card interface entering in power-down mode in order to reduce the power consumption, a power-down or idle mode can be invoked by software (see table 13, pcon register). before activating these modes the applica- tion will need to: power-off the smart card interface by applying the following sequence: ? set crst pin at low level by clearing the bit cardrst in sccon register. ? set cclk pin at low level by clearing the bit clk then the cardclk in sccon register. ? set cio pin at low level by clearing the bit uart in scicr register then the bit cardio in sccon register. ? power the smart interface of f by clearing the cardvcc bit in sccon register. this instruction enables to s witch dc/dc converter off. cpres input: ? set the bit prsen in isel register ? set the bit ex1 in ie0 register ? set the bit ea in the ie0 register ? invert the bit cplev in isel register (int1 interrupt vector) ? clear the bit presit in the isel register exiting from power-down mode the microcontroller will exit fr om power-down or idle modes upon a reset or int1 inter- rupt which is a multiplexing of the interruptions genera ted by the cpres pin (card detection), rxd flag (uart reception) and int1 pin. usb controller init detection of a suspend state spint set suspclk disable pll microcontroller in power-down detection of a resume state wupcpu enable pll clear suspclk clear wupcpu bit clear spint note : wupcpu bit must be cleared before enabling the pll put the usb pads in power down mode
184 at8xc5122/23 4202d?scr?06/05 keyboard interface the keyboard interface applies only to at8xc5122 version. entering in power-down mode in order to reduce the power consumption, the microcontroller can be set in power-down or idle mode by software (see table 13, pcon register). before activating these modes the application will need to configure the keyboard interface as follows: ? set all keyboard?s ouputs pins kb rx at low level by writing a 0 on the ports. this operation has a double effect: ? any key that is pressed generates an interrupt capable of waking-up the microcontroller, ? set all bits kbe.x in kbe regi sters to enable interrupts. exiting from power-down mode the microcontroller will exit fr om power-down mode upon a re set or any interrupt gener- ated by a key press. note that 1024 clocks are necessary to exit from power-down mode when a keyboard interru pt occurs. this means that th ere will be a delay between the time at which the key is pressed and the time at which the application is able to identify the key. watchdog timer during power-down and idle mode in power-down mode the oscillator stops, which means the wdt also stops. while in power-down mode the user does not need to service the wdt. there are 2 methods of exiting power-down mode : by a hardware reset or by a level activated external interrupt which is enabled prior to entering power- down mode. when power-down is exited with hardware reset, servicing the wdt should occur as it normally does whenever at8xc5122d is reset. exiting power-down with an interrupt is significantly different. the interrupt is held low long enough for the osci llator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrup t pin is held low, the wdt is not star ted until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service for the interrupt used to exit power-down. to ensure that the wdt does not overflow within a few states of exiting of powerdown, it is best to reset the wdt just before entering powerdown. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting while the microcontroller is in idle mode, t he user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode.
185 at8xc5122/23 4202d?scr?06/05 registers reset value = 00x1 0000b power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesn?t affect the value of this bit. table 113. power control register - pcon (s:87h) 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 for uart set to select double baud rate in mode 1,2 or 3 6smod0 serial port mode bit 0 for uart cleared to select sm0 bit in scon register set to select fe bit in scon register 5- reserved the value read from this bit is i ndeterminate. do not change this bit. 4pof power-off flag (only for rom version parts) cleared to recognize next reset type set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software warning : in cram and flash versions, this bit is reserved. 3gf1 general purpose flag cleared by user for general-purpose usage set by user for general-purpose usage 2gf0 general purpose flag cleared by user for general-purpose usage set by user for general-purpose usage 1pd power-down mode bit cleared by hardware when reset occurs set to enter power-down mode 0idl idle mode bit cleared by hardware when interrupt or reset occurs set to enter idle mode
186 at8xc5122/23 4202d?scr?06/05 electrical characteristics absolute maximum ratings dc parameters t a = -40 to +85 c; v ss = 0 v, f ck_cpu = 0 to 24 mhz , v cc = 3.6v to 5.5v ambiant temperature under bias ............ ..........-25 c to 85 c storage temperature .................................... -65 c to + 150 c voltage on v cc to v ss ......................................-0.5 v to + 6.0v voltage on any pin to v ss ........................-0.5 v to v cc + 0.5 v power dissipation 1 w note: stresses at or above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indica ted in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage: p0, ale, psen 0.45 v i ol = 1.6 ma v oh output high voltage: p0, ale, psen 0.9 v cc vi oh = 10 a v ol1 output low voltage: p2, p3, p4, p5, p1.2, p1.6, p1.7 0.45 v i ol = 0.8 ma v oh1 output high voltage: p2, p3, p4, p5, p1.2, p1.6, p1.7 0.9 v cc vi oh = -10 a i il logical 0 input current ports 2 to 5 and p1.2, p1.6, p1.7, if weak pull-up enabled -50 a vin = 0.45 v i li input leakage current 10 a 0.45 v < v in < v cc i tl logical 1 to o transistion current, port 51 configuration ? 650 av in = 2 v r medium medium pullup resistor 10 k ? r weak weak pullup resistor 100 k ? cio capacitance of i/o buffer 10 pf fc = 1mhz t a = 25 c dv cc digital supply voltage 3 3.4 3.6 v c l = 470 nf di cc digital supply output current (dvcc pin) 10 ma c l = 100 nf f ck_cpu = 24 mhz v pfdp power fail high level threshold 2.8 3 v v pfdm power fail low level threshold 2,5 2.6 v t rise, t fall v dd rise and fall time 1 s 600 second
187 at8xc5122/23 4202d?scr?06/05 r rst internal reset pull-up resistor 5 10 30 k ? i pd power down consumption 60a 40a 200a 200a vcc = 5.5v vcc = 3.6v i ccidle power supply current in idle mode 0.4*f+2 ma vcc = 5.5v (f in mhz) i ccop power supply current in active mode (at89c5122) with dc/dc on 1.6*f+3 ma vcc = 5.5v (f in mhz) i ccop power supply current in active mode (AT85C5122) with dc/dc on 1.6*f+3 ma vcc = 5.5v (f in mhz) i ccop power supply current in active mode (at83c5122) with dc/dc on 1.6*f+2 ma vcc = 5.5v (f in mhz) i ccwrite power supply current in active mode (at89c5122) flash or e2prom write dc/dc on 1.6*f+4 ma vcc = 5.5v (f in mhz) i ccop power supply current in active mode (at89c5122) with dc/dc off 0.8*f+3 ma vcc = 5.5v (f in mhz) i ccop power supply current in active mode (AT85C5122) with dc/dc ff 0.8*f+3 ma vcc = 5.5v (f in mhz) i ccop power supply current in active mode (at83c5122) with dc/dc off 0.8*f+2 ma vcc = 5.5v (f in mhz) i ccwrite power supply current in active mode (at89c5122) flash or e2prom write dc/dc off 0.8*f+4 ma vcc = 5.5v (f in mhz) symbol parameter min typ max unit test conditions
188 at8xc5122/23 4202d?scr?06/05 i cc current test conditions figure 111. power down mode figure 112. active and idle mode led?s note: 1. (t a = -20 c to +50 c, v cc - v ol = 2 v ) all other pins are disconnected. ea ipd v cc v cc (nc) p0 xtal2 xtal1 vss v cc pllf gnd gnd li av cc gnd avss v cc gnd all other pins are disconnected. ea v cc icc v cc v cc (nc) p0 xtal2 xtal1 vss v cc clock signal pllf gnd gnd li av cc gnd avss symbol parameter min typ max unit test conditions i ol output low current, p3.6 and p3.7 led modes 1 2 5 3 6 10 5 8 20 ma ma ma 2 ma configuration 4 ma configuration 10 ma configuration
189 at8xc5122/23 4202d?scr?06/05 smart card interface card vcc 5v (for ie c7816-3 class a cards) symbol parameter min typ max unit test conditions vcc power supply 4.0 5.5 v ci cc_ovf card supply current overflow 100 ma cv cc card supply voltage 4.6 5.4 v ci cc = 60 ma ripple on card voltage 200 mv 0 < cicc < 60 ma cv cc card supply voltage during spike on icc 4.5 5.5 max. charge 20 na.s max. duration 400 ns max. variation ci cc 100 ma t off cvcc to 0 750 s cload=10f, lload=10h vcard = cvcc to 0.4v t on 0 to cvcc 750 s cload=10f, lload=10h vcard = 0v to cvcc with boost at 60% card vcc 3v power supply (f or iec7816-3 class b cards) symbol parameter min typ max unit test conditions vcc power supply 3.6 5.5 v ci cc_ovf card supply current overflow 100 ma cv cc card supply voltage 2.76 3.24 v ci cc = 60 ma ripple on vcard 200 mv 0 < ci cc < 60 ma cv cc card supply voltage during spike on icc 2.7 3.3 v maxi. charge 10na.s max. duration 400 ns max. variation ci cc 50ma t off cvcc to 0 750 s cload=10f, lload=10h vcard = cvcc to 0.4v t on 0 to cvcc 750 s cload=10f, lload=10h vcard = 0v to cvcc with boost at 60%
190 at8xc5122/23 4202d?scr?06/05 notes: 1. test conditions, capacitor 10 f, inductance 10 h. 2. ceramic x7r, smd type capacitor with minimum esr or 250 m ? is mandatory notes: 1. the voltage on clk should remain between -0.3v and v cc +0.3v during dynamic operation. card vcc 1.8v power supply (for iec7816-3 class c cards) symbol parameter min typ max unit test conditions vcc power supply 3.6 5.5 v ci cc_ovf card supply current overflow 100 ma cv cc card supply voltage 1.68 1.92 v ci cc = 30 ma t off cvcc to 0 750 s cload=10f, lload=10h vcard = cvcc to 0.4v t on 0 to cvcc 750 s cload=10f, lload=10h vcard = 0v to cvcc with boost at 60% smart card cclk, dc parameters symbol parameter min typ max unit test conditions v ol output low voltage 0 (1) 0 (1) 0.2xv cc 0.4 vi ol = 20 ? (1.8v, 3v) i ol = 50 a (5v) i ol output low current 15 ma v oh output high voltage 0.7 cv cc 0.7 cv cc 0.7 cv cc cv cc - 0.5 cv cc cv cc cv cc cv cc v v v v i oh = 20 a (1.8v) i oh = 20 a (3v) i oh = 20 a (5v) i oh = 50 a (5v) i oh output high current 15 ma t r t f rise and fall delays 16 22.5 50 ns c in =30pf (5v) c in =30pf (3v) c in =30pf (1.8v) voltage stability -0.25 cv cc -0.5 0.4 cv cc cv cc + 0.25 v low level high level frequency variation 1% cycle ratio 45% 55% smart card cio, dc parameters symbol parameter min typ max unit test conditions v il input low voltage 0 (1) 0 (1) 0.5 0.15 cv cc v i il = 500 a i il = 20 a i il input low current 500 a v ih input high voltage 0.7 cv cc cv cc vi ih = -20 a i ih input high current -20 / +20 a v ol output low voltage 0 (1) 0.4 0.4 0.3 v i ol = 1ma (5v) i ol = 1ma (3v) i ol = 1ma (1.8v)
191 at8xc5122/23 4202d?scr?06/05 note: 1. the voltage on rst should remain between -0.3v and v cc +0.3v during dynamic operation. note: 1. the voltage on rst should remain between -0.3v and v cc +0.3v during dynamic operation. i ol output low current 15 ma v oh output high voltage 0.8 cv cc 0.7 cv cc cv cc (1) v i oh = 20 a (5v) i oh = 20 a (3v, 1.8v) i oh output high current 15 ma voltage stability -0.25 0.8 cv cc 0.4 cv cc + 0.25 vlow level high level t r t f rise and fall delays 0.8 sc in =30pf. smart card rst, cc4, cc8, dc parameters symbol parameter min typ max unit test conditions v ol output low voltage 0 (1) 0 (1) 0.12 x v cc 0.4 v i ol = 20 ? i ol = 50 ? i ol output low current 15 ma v oh output high voltage cv cc - 0.5 0.8 x v cc cv cc cv cc (1) v i oh = 50 ? i oh = 20 ? i oh output high current 15 ma t r t f rise and fall delays 0.8 sc in =30 pf voltage stability -0.25 cv cc -0.5 0.4 x cv cc cv cc + 0.25 low level high level smart card cio, dc parameters symbol parameter min typ max unit test conditions card presence (p1.2) dc parameters symbol parameter min typ max unit test conditions i ol1 cpres weak pull-up output current 3 10 25 a p1.2=1, short to vss pull-up enabled
192 at8xc5122/23 4202d?scr?06/05 usb interface figure 113. usb interface symbol parameter min typ (5) max unit v ref usb reference voltage 3.0 3.6 v v ih input high voltage for d+ and d- (driven) 2.0 4.0 v v ihz input high voltage for d+ and d- (floating) 2.7 3.6 v v il input low voltage for d+ and d- 0.8 v v oh output high voltage for d+ and d- 2.8 3.6 v v ol output low voltage for d+ and d- 0.0 0.3 v
193 at8xc5122/23 4202d?scr?06/05 ac parameters explanation of the ac symbols each timing symbol has 5 characters. the fi rst character is always a ?t? (stands for time). the other characters, depending on thei r positions, stand for the name of a signal or the logical status of that signal. the foll owing is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a = -40 c to +85 c; v ss = 0v; v cc = 3.6v to 5.5v ; f ck_cpu = 0 to 24 mhz. (load capacitance for port 0, ale and psen = 60 pf; load capacitance for all other outputs = 60 pf.) table and table 118 give the de scription of each ac symbols. table 117 and table 120 give for each range the ac parameter. table 115, table 117 and table 119 give the frequency derating formula of the ac parameter for each speed range description. to calculate each ac symbols. take the x value and use this value in the formula. example: t lliv and 20 mhz, standard clock. x = 30 ns t = 50 ns t cciv = 4t - x = 170 ns external program memory characteristics table 114. symbol description symbol parameter t cpu clock period (f ck_cpu ) t lhll ale pulse width t avll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction float after psen t aviv address to valid instruction in t plaz psen low to address float
194 at8xc5122/23 4202d?scr?06/05 external program memory read cycle table 115. ac parameters for a variable clock symbol type standard clock x2 clock x parameter units t lhll min 2t - x t - x 15 ns t avll min t - x 0.5 t - x 20 ns t llax min t - x 0.5 t - x 20 ns t lliv max 4t - x 2 t - x 35 ns t llpl min t - x 0.5 t - x 15 ns t plph min 3t - x 1.5 t - x 25 ns t pliv max 3t - x 1.5 t - x 45 ns t pxix min x x 0 ns t pxiz max t - x 0.5 t - x 15 ns t aviv max 5t - x 2.5 t - x 45 ns t plaz max x x 10 ns 12 t clcl t lliv t lhll t llpl ale t plph psen port 0 instr in a0-a7 instr in a0-a7 instr in t llax tplaz t pxav t avll t pxix t pxiz t pliv t aviv port 2 address or sfr-p2 address a8-a15 address a8-a15
195 at8xc5122/23 4202d?scr?06/05 external data memory characteristics table 116. symbol description symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t avdv address to valid data in t llwl ale to wr or rd t avwl address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high
196 at8xc5122/23 4202d?scr?06/05 table 117. ac parameters for a variable clock (warning x value differ from at89c51rd2) external data memory write cycle symbol type standard clock x2 clock x parameter units t rlrh min 6t - x 3 t - x 20 ns t wlwh min 6t - x 3 t - x 20 ns t rldv max 5t - x 2.5 t - x 25 ns t rhdx min x x 0 ns t rhdz max 2t - x t - x 20 ns t lldv max 8t - x 4t - x 40 ns t avdv max 9t - x 4.5 t - x 60 ns t llwl min 3t - x 1.5 t - x 25 ns t llwl max 3t + x 1.5 t + x 25 ns t avwl min 4t - x 2 t - x 25 ns t qvwx min t - x 0.5 t - x 15 ns t qvwh min 7 t - x 3.5 t - x 25 ns t whqx min t - x 0.5 t - x 10 ns t rlaz max x x 0 ns t whlh min t - x 0.5 t - x 15 ns t whlh max t - x 0.5 t + x 15 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh
197 at8xc5122/23 4202d?scr?06/05 external data memory read cycle serial port timing - shift register mode table 118. symbol description (f = 40 mhz) table 119. ac parameters for a variable clock ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t llax t avdv symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid symbol type standard clock x2 clock x parameter units t xlxl min 12t 6 t ns t qvhx min 10t - x 5 t - x 50 ns t xhqx min 2t - x t - x 20 ns t xhdx min x x 0 ns t xhdv max 10t - x 5 t- x 133 ns
198 at8xc5122/23 4202d?scr?06/05 shift register timing waveform external clock drive characteristics (xtal1) table 120. ac parameters external clock drive waveforms ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. timing measurement are made at v ih min for a logic ?1? and v il max for a logic ?0?. valid valid valid valid valid valid input data valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid symbol parameter min max units t clcl oscillator period 125 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5v 0.45v
199 at8xc5122/23 4202d?scr?06/05 float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20 ma. clock waveforms valid in normal clock mode. in x2 mode xtal2 must be changed to xtal2/2. float v oh - 0.1 v v ol + 0.1 v v load v load + 0.1 v v load - 0.1 v data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if progra m memory is externa l old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled
200 at8xc5122/23 4202d?scr?06/05 this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperatur e and pin loading. pr opagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. usb interface rise time fall time v crs differential data lines 90% 10% 90% 10% t r t f v hmin v lmax symbol parameter min typ (5) max unit t r rise time 4 20 ns t f fall time 4 20 ns t fdrate full-speed data rate 11.9700 12.0300 mb/s v crs crossover voltage 1.3 2.0 v t dj1 source jitter total to next transaction -3.5 3.5 ns t dj2 source jitter total for paired transactions -4 4 ns t jr1 receiver jitter to next transaction -18.5 18.5 ns t jr2 receiver jitter for paired transactions -9 9 ns
201 at8xc5122/23 4202d?scr?06/05 packaging information ordering information standard part number lead free/ rohs part number memory size (bytes) supply voltage (v) temperature range max frequency (mhz) package packing at83c5122xxx-rdtim at83c5122xxx-r dtum 32k rom 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tray at83c5122xxx-rdrim at83c5122xxx-rdrum 32k rom 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tape & reel at83c5122xxx-sisim at83c5122xxx-sisum 32k rom 3.6 - 5.5 industrial 48 mhz / x1 plcc28 stick at83c5122xxx-sirim at83c5122xxx-surim 32k rom 3.6 - 5.5 industrial 48 mhz / x1 plcc28 tape & reel at83c5122xxx-psvim at83c5122xxx-pstum 32k rom 3.6 - 5.5 industrial 48 mhz / x1 qfn64 tray & dry pack at83c5122xxx-psfim at83c5122xxx-psrum 32k rom 3.6 - 5.5 industrial 48 mhz / x1 qfn64 tape & reel & dry pack at83ec5122xxx-rdvim at83ec5122xxx-rdtum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tray & dry pack at83ec5122xxx-rdfim at83ec5122xxx- rdrum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tape & reel & dry pack at83ec5122xxx-psvim at83ec5122xxx-pstum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 qfn64 tray & dry pack at83ec5122xxx-psfim at83ec5122xxx-psrum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 qfn64 tape & reel & dry pack AT85C5122d-rdtim AT85C5122d-rdtum 32k cram 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tray AT85C5122d-rdrim AT85C5122d-rdrum 32k cram 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tape & reel AT85C5122d-sisim AT85C5122d-sisum 32k cram 3.6 - 5.5 industrial 48 mhz / x1 plcc28 stick AT85C5122d-sirim AT85C5122d-sirum 32k cram 3.6 - 5.5 industrial 48 mhz / x1 plcc28 tape & reel at89c5122d-rdvim (1) at89c5122d-rdtum 32k flash 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tray & dry pack at89c5122d-rdfim (1) at89c5122d-rdrum 32k flash 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tape & reel & dry pack at89c5122d-psvim at89c5122d-pstum 32k flash 3.6 - 5.5 industrial 48 mhz / x1 qfn64 tray & dry pack at89c5122d-psfim at89c5122d-psrum 32k flash 3.6 - 5.5 industrial 48 mhz / x1 qfn64 tape & reel & dry pack
202 at8xc5122/23 4202d?scr?06/05 note: 1. check avaibility with sales office at89c5122ds-rdvim at89c5122ds-rdtum 32k flash 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tray & dry pack at89c5122ds-rdfim at89c5122ds-rdrum 32k flash 3.6 - 5.5 industrial 48 mhz / x1 vqfp64 tape & reel & dry pack at89c5122ds-psvim at89c5122d-pstum 32k flash 3. 6 - 5.5 industrial 48 mhz / x1 qfn64 tray & dry pack at89c5122ds-psfim at89c5122d-psrum 32k flash 3.6 - 5.5 industrial 48 mhz / x1 qfn64 tape & reel & dry pack at83c5123xxx-ratim at83c5123xxx-ratum 30k rom 3.6 - 5.5 industrial 48 mhz / x1 vqfp32 tray at83c5123xxx-rarim at83c5123xxx-rarum 30k rom 3.6 - 5.5 industrial 48 mhz / x1 vqfp32 tape & reel at83c5123xxx-sisim at83c5123xxx-sisum 30k rom 3.6 - 5.5 industrial 48 mhz / x1 plcc28 stick at83c5123xxx-sirim at83c5123xxx-sirum 30k rom 3.6 - 5.5 industrial 48 mhz / x1 plcc28 tape & reel at83c5123xxx-putim at83c5123xxx-putum 30k rom 3.6 - 5.5 industrial 48 mhz / x1 qfn32 tray at83c5123xxx-purim at83c5123xxx-purum 30k rom 3.6 - 5.5 industrial 48 mhz / x1 qfn32 tape & reel at83ec5123xxx-ravim at83ec5123xxx-ratum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 vqfp32 tray & dry pack at83ec5123xxx-rafim at83ec5123xxx-rarum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 vqfp32 tape & reel & dry pack at83ec5123xxx-puvim at83ec5123xxx-putum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 qfn32 tray & dry pack at83ec5123xxx-pufim at83ec5123xxx-purum 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 48 mhz / x1 qfn32 tape & reel & dry pack standard part number lead free/ rohs part number memory size (bytes) supply voltage (v) temperature range max frequency (mhz) package packing
203 at8xc5122/23 4202d?scr?06/05 mechanical dimensions plcc28 package
204 at8xc5122/23 4202d?scr?06/05 vqfp64 package
205 at8xc5122/23 4202d?scr?06/05 plcc68 package
206 at8xc5122/23 4202d?scr?06/05 vqfp32 package
207 at8xc5122/23 4202d?scr?06/05 qfn32 package
208 at8xc5122/23 4202d?scr?06/05 qfn64 package
209 at8xc5122/23 4202d?scr?06/05 change log changes from 4202a to 4202b 1. product at8xec5122 added. 2. products at83c5123 and at83ec5123 added. changes from 4202b to 4202c 1. all sections updated. 2. qfn64 and qfn32 packages added. 3. scib section : vcc must be higher than 4.0v when dc/dc is operated at 5v. changes from 4202c to 4202d 1. product at89c5122ds added (ea pin changed to vcc) 2. typical applications section: external pull-up shown on cio pin 3. ports section : detailed explanations on cio, cc4, cc8 quasi-bidirectional ports 4. ordering information section: at89c5122ds part-numbers added
210 4202d?scr?06/05 at8xc5122/23 table of contents features .............. .............. .............. .............. .............. .............. ............. 1 reference documents .......................................................................................... 2 product description .............................................................................................. 3 at8xc5122 block diagram .......................... ........................................................ 5 at83c5123 block diagram ......................... ......................................................... 5 pinout ................. .............. .............. .............. .............. .............. ............. 6 high pin count package description......... ........................................................... 6 low pin count package description .................................................................. 11 pin description.................................................................................................... 13 typical applications ........ .............. .............. .............. .............. ........... 17 recommended external components .................................................................17 usb keyboard with smart card reader using the at8xc5122 and at89c5122ds ver- sions .......................................................................................................................... ... 18 usb smart card reader usin g the at83c5123 version.................................... 19 memory organization ........ .............. .............. .............. .............. ......... 20 program memory managament .......................................................................... 20 data memory managament .... ............................................................................ 21 dual data pointer register (ddptr) ..... ............................................................ 22 registers............................................................................................................. 24 at8xc5122?s cram and e2prom versions ..................................................... 26 at8xc5122?s rom version ................................................................................ 30 at83c5123 version ............................................................................................ 32 special function registers (sfr?s) ...... ................. ................ ........... 33 introduction ......................................................................................................... 33 at8xc5122 version............................................................................................ 34 at83c5123 version ........................................................................................... 35 sfr?s description ............................................................................................... 36 clock controller ............... .............. .............. .............. .............. ........... 41 on-chip oscillator .............................................................................................. 41 phase lock loop (pll) ...................................................................................... 42 clock tree architecture ...................................................................................... 43 registers............................................................................................................. 50 i/o port definition ..... ................ ................ ................. .............. ........... 53 port configuration............................................................................................... 57 registers............................................................................................................. 61 smart card interface block (scib) ....... ................. ................ ........... 64 block diagram .................................................................................................... 65
211 4202d?scr?06/05 at8xc5122/23 definitions ........................................................................................................... 65 functional description ........................................................................................ 67 additional features............................................................................................. 74 alternate card..................................................................................................... 78 registers ............................................................................................................. 78 dc/dc converter................................................................................................ 88 usb controller ................. .............. .............. .............. .............. ........... 95 description.......................................................................................................... 96 configuration ...................................................................................................... 99 read/write data fifo ...................................................................................... 102 bulk / interrupt transactions............................................................................. 103 control transactions......................................................................................... 107 isochronous transactions... .............................................................................. 108 miscellaneous ................................................................................................... 110 suspend/resume management .......................................................................111 detach simulation............................................................................................. 114 usb interrupt system ....................................................................................... 115 registers........................................................................................................... 117 serial i/o port ....... ................ ................. ................ ................. ........... 126 framing error detection ......................... .......................................................... 126 automatic address recognition................. ....................................................... 127 asynchronous modes (modes 1, 2 and 3) ........................................................ 131 modes 2 and 3 .................................................................................................. 132 registers........................................................................................................... 135 serial port interface (spi) ................. .............. ............... ........... ....... 137 features............................................................................................................ 137 signal description............................................................................................. 137 functional description ...................................................................................... 139 timers/counters ....... ................ ................ ................. .............. ......... 147 timer/counter operations ................................................................................ 147 timer 0.............................................................................................................. 147 timer 1.............................................................................................................. 150 registers........................................................................................................... 152 keyboard interface ............ .............. .............. .............. .............. ....... 155 introduction ....................................................................................................... 155 description........................................................................................................ 155 registers........................................................................................................... 156 interrupt system .............. .............. .............. .............. .............. ......... 159 introduction ....................................................................................................... 159 interrupt system descriptio n ............................................................................ 159
212 4202d?scr?06/05 at8xc5122/23 registers........................................................................................................... 162 interrupt sources and vector s .......................................................................... 171 microcontroller reset ........ .............. .............. .............. .............. ....... 172 introduction ....................................................................................................... 172 power on reset (por) .................................................................................... 173 power fail detector (pfd).. .............................................................................. 173 reset pin........................................................................................................... 175 watchdog timer ............................................................................................... 177 power management .... ................ ................. .............. .............. ......... 180 idle mode .......................................................................................................... 180 power down mode ........................................................................................... 180 reduced emi mode .......................................................................................... 181 usb interface ................................................................................................... 182 smart card interface .......... .............................................................................. 183 keyboard interface ........................................................................................... 184 watchdog timer during powe r-down and idle mode........................................ 184 registers........................................................................................................... 185 electrical characteristics .... ................. ................ ................. ........... 186 absolute maximum ratings ...................... ........................................................186 dc parameters .................................................................................................186 led?s ................................................................................................................188 smart card interface .......... .............................................................................. 189 usb interface ................................................................................................... 192 ac parameters ................................................................................................. 193 float waveforms............................................................................................... 199 packaging information ........ ................. ................ ................. ........... 201 ordering information......................................................................................... 201 mechanical dimensions.................................................................................... 203 change log ............... ................ ................ ................. .............. ......... 209 changes from 4202a to 4202b ........................................................................209 changes from 4202b to 4202c ........................................................................209 changes from 4202c to 4202d ........................................................................209 table of contents ............ .............. .............. .............. .............. ......... 210
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